scholarly journals Design of a Fault Tolerant Razor Flip Flop Sklansky Adder for Delay Reduction in FIR Filter

2019 ◽  
Vol 8 (9) ◽  
pp. 2647-2651
Keyword(s):  
Fault Tolerance ◽  
High Performance ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Fir Filter ◽  
Delay Reduction ◽  
Flip Flop ◽  
Multiple Faults ◽  
Fault Tolerant System ◽  
Logic Unit

Basically, to reduce the failure rate in the system, we need to introduce the fault tolerant system. Because of multiple faults occurred in the system, the system will increase the area. To employ the adder architecture, different algorithms are used in digital signal processing. By introducing the fault tolerant system, the reliability of the proposed system will increase. So in this paper we introduced the design of fault tolerant razor flip flop using SKLANSKY adder for delay reduction in FIR filter. The razor flip flop will increase the energy efficiency of proposed system. This flip flop will store the information by latching the circuit. The SKLANSKY adder is the part of arithmetic logic unit. In proposed system, all bits are summed and followed to the fault tolerance system,. This fault tolerance system will detect the error and give efficient output. Hence compared to existed system, the proposed system gives high performance and accuracy in terms of delay.

Issues of organizing computations in multicomputersystems with the software-controlled failure- and fault-tolerance. Part 1

2021 ◽  
Author(s):  
I.V. Asharina
Keyword(s):  
Fault Tolerance ◽  
Critical Level ◽  
Fault Tolerant ◽  
Communication Channels ◽  
State Standards ◽  
Modern Concept ◽  
Multiple Faults ◽  
Point To Point ◽  
Definition Of ◽  
Test Diagnostics

This three-part paper analyzes existing approaches and methods of organizing failure- and fault-tolerant computing in distributed multicomputer systems (DMCS), identifies and provides rationale for a list of issues to be solved. We present the concept of fault tolerance proposed by A. Avizienis, explicate its dissimilarity from the modern concept and the reason for its inapplicability with regard to modern distributed multicomputer systems. We justify the necessity to refine the definition of fault tolerance approved by the State Standards, as well as the necessity to specify three input parameters to be taken into account in the DMCS design methods: permitted fault models, permitted multiplicity of faults, permitted fault sequence capabilities. We formulate the questions that must be answered in order to design a truly reliable, fault-tolerant system and consider the application areas of the failure- and fault-tolerant control systems for complex network and distributed objects. System, functional, and test diagnostics serve as the basis for building unattended failure- and fault-tolerant systems. The concept of self-managed degradation (with the DMCS eventually proceeding to a safe shutdown at a critical level of degradation) is a means to increase the DMCS active life. We consider the issues related to the diagnosis of multiple faults and present the main differences in ensuring fault tolerance between systems with broadcast communication channels and systems with point-to-point communication channels. The first part of the work mainly deals with the analysis of existing approaches and methods of organizing failure- and fault-tolerant computing in DMCS and the definition of the concept of fault-tolerance.

A RECONFIGURATION TECHNIQUE FOR RELIABLE VLSI DSP ARRAY PROCESSORS

1992 ◽  
Vol 02 (03) ◽  
pp. 281-304
Author(s):  
SANJAY P. POPLI ◽  
MAGDY A. BAYOUMI ◽  
AKASH TYAGI
Keyword(s):  
Fault Tolerance ◽  
Error Detection ◽  
High Performance ◽  
Interconnection Network ◽  
Digital Signal ◽  
Design Criterion ◽  
Fault Detection And Diagnosis ◽  
Detection Technique ◽  
Concurrent Error Detection ◽  
Tolerance Strategy

Real-time digital signal processing (DSP) applications require high performance parallel architectures that are also reliable. VLSI arrays are good candidates for providing the required high throughput for these applications. These arrays which consist of a number of regularly interconnected processing elements (PEs) will not function correctly in the presence of even a single fault in any of the PEs. Fault tolerance has therefore become a vital design criterion for VLSI arrays. In this paper, a fault tolerance strategy for VLSI arrays is proposed, which significantly improves the reliability of the system. The fault tolerance scheme is composed of two phases: testing and locating faults (fault detection and diagnosis), and reconfiguration. The first phase employs an on-line error detection technique which achieves a compromise between the space and time redundancy approaches. This concurrent error detection technique reduces the rollback time considerably. The reconfiguration phase is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. Finally, a reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.

scholarly journals The advancement of cluster based FPGA place & route technic

2020 ◽  
Vol 309 ◽  
pp. 01014
Author(s):  
Zhimei Zhou ◽  
Yong Wan ◽  
Yin Liu ◽  
Xiaoyan Guo ◽  
Qilin Yin ◽  
...  
Keyword(s):  
Information Technology ◽  
High Speed ◽  
High Performance ◽  
Design Method ◽  
Digital Signal ◽  
Programmable Logic ◽  
Logic Block ◽  
Chip Technology ◽  
Routing Technology ◽  
Logic Unit

As one of the core components of electronic hardware systems, Field Programmable Logic Array (FPGA) device design technology continues to advance under the guidance of electronic information technology policies, and has made information technology applications. huge contribution. However, with the advancement of chip technology and the continuous upgrading of information technology, the functions that FPGAs need to perform are more and more complicated. How to efficiently perform layout design and make full use of chip resources has become an important technology to be solved and optimized in FPGA design. The FPGA itself is not limited to a specific function. It contains internal functions such as memory, protocol module, clock module, high-speed interface module and digital signal processing. It can be programmed through logic modules such as programmable logic unit modules and interconnects. Blank FPGA devices are designed to be high performance system applications with complex functions. The layout and routing technology based on cluster logic unit blocks can combine the above resources to give full play to its performance advantages, and its importance is self-evident. Based on the traditional FPGA implementation, this paper analyzes several advantages based on cluster logic block layout and routing technology, and generalizes the design method and flow based on cluster logic block layout and routing technology.

scholarly journals Transparent fault tolerance for scalable functional computation

2016 ◽  
Vol 26 ◽  
Author(s):  
ROBERT STEWART ◽  
PATRICK MAIER ◽  
PHIL TRINDER
Keyword(s):  
Fault Tolerance ◽  
High Performance Computing ◽  
High Performance ◽  
Large Scale ◽  
Programming Model ◽  
Fault Tolerant ◽  
Fault Recovery ◽  
Actor Model ◽  
Work Stealing ◽  
Performance Computing

AbstractReliability is set to become a major concern on emergent large-scale architectures. While there are many parallel languages, and indeed many parallel functional languages, very few address reliability. The notable exception is the widely emulated Erlang distributed actor model that provides explicit supervision and recovery of actors with isolated state. We investigate scalable transparent fault tolerant functional computation with automatic supervision and recovery of tasks. We do so by developing HdpH-RS, a variant of the Haskell distributed parallel Haskell (HdpH) DSL with Reliable Scheduling. Extending the distributed work stealing protocol of HdpH for task supervision and recovery is challenging. To eliminate elusive concurrency bugs, we validate the HdpH-RS work stealing protocol using the SPIN model checker. HdpH-RS differs from the actor model in that its principal entities are tasks, i.e. independent stateless computations, rather than isolated stateful actors. Thanks to statelessness, fault recovery can be performed automatically and entirely hidden in the HdpH-RS runtime system. Statelessness is also key for proving a crucial property of the semantics of HdpH-RS: fault recovery does not change the result of the program, akin to deterministic parallelism. HdpH-RS provides a simple distributed fork/join-style programming model, with minimal exposure of fault tolerance at the language level, and a library of higher level abstractions such as algorithmic skeletons. In fact, the HdpH-RS DSL is exactly the same as the HdpH DSL, hence users can opt in or out of fault tolerant execution without any refactoring. Computations in HdpH-RS are always as reliable as the root node, no matter how many nodes and cores are actually used. We benchmark HdpH-RS on conventional clusters and an High Performance Computing platform: all benchmarks survive Chaos Monkey random fault injection; the system scales well e.g. up to 1,400 cores on the High Performance Computing; reliability and recovery overheads are consistently low even at scale.

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

scholarly journals Methods for building a high-performance fault-tolerant distributed database for the task of perimeter security

2021 ◽  
pp. 55-62
Author(s):  
Андрей Иванович Костюк ◽  
Наталия Михайловна Коробейникова
Keyword(s):  
Fault Tolerance ◽  
Performance Indicators ◽  
System Performance ◽  
High Performance ◽  
Fault Tolerant ◽  
Key Performance Indicators ◽  
Distributed Database ◽  
Security Problem ◽  
Key Indicators

Описаны методы построения высокопроизводительной отказоустойчивой распределенной базы данных для задачи охраны периметра. Представлена архитектура подсистемы отказоустойчивости, архитектура подсистемы резервного копирования, описаны подходы к достижению заданных ключевых показателей. Проведено исследование производительности системы, определены ключевые показатели эффективности, достигаемые подсистемой обеспечения отказоустойчивости. The paper discusses the methods for constructing a high-performance fault-tolerant distributed database for the perimeter security problem. The architecture of the fault tolerance subsystem, the architecture of the backup subsystem, and approaches to achieving the specified key indicators are described. The study of the system performance was carried out, the values of the key performance indicators achieved by the fault tolerance subsystem were determined.

scholarly journals Design and Implementation of Hybrid FIR Filters using Vedic Multiplier and Fast Adders

2019 ◽  
Vol 8 (4) ◽  
pp. 11849-11853
Keyword(s):  
High Speed ◽  
High Performance ◽  
Noise Suppression ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Vital Role ◽  
Finite Impulse Response Filters ◽  
Vedic Multiplier ◽  
Impulse Response Filters

FIR (Finite Impulse Response) filters play a significant role in the field of Digital Signal Processing (DSP) to eliminate noise suppression in Electro Cardio Graph (ECG), Imaging devices and the signal stored in analog media. So filter evaluation is accomplished to reduce the noise level. The Filter passes only the desired frequency to pass thereby reducing distortion in the processed signal during measurement. The FIR filter comprises of basic units like adders, multipliers and the delay element for its operations.FIR and IIR are the two types of digital filters chosen based on the range of inputs, complexity and size requirement. Multipliers and adders play a vital role in deterring the performance of FIR filter. In this work, we design and analyze different multiplier and adder for high-performance Fir filter implementation. The Vedic Mathematics is the methods containing 16 Sutras to aid fast mental calculations. In this work, we propose modified Anurupye Vedic multiplier methods with Kogge Stone fast adder for implementation in the direct form FIR filter. This approach provides 1.5% decrease in delay and 10.2% reduced in power, hence increasing speed marginally than previous methods. Along with low power consumption in Very High-Speed Hardware Description Language (VHDL), all the adders and the multiplier topologies are Synthesized using (Xilinx Spartan – 6 FPGA) Trainer Kit and the proposed 8 – Tap FIR filter is executed using this Board

Fault Tolerance Techniques for Distributed, Parallel Applications

2016 ◽  
pp. 221-252
Author(s):  
Camille Coti
Keyword(s):  
Fault Tolerance ◽  
High Performance Computing ◽  
High Performance ◽  
Fault Tolerant ◽  
Distributed Applications ◽  
Parallel Applications ◽  
Rollback Recovery ◽  
Tolerance Mechanisms ◽  
Performance Computing

This chapter gives an overview of techniques used to tolerate failures in high-performance distributed applications. We describe basic replication techniques, automatic rollback recovery and application-based fault tolerance. We present the challenges raised specifically by distributed, high performance computing and the performance overhead the fault tolerance mechanisms are likely to cost. Last, we give an example of a fault-tolerant algorithm that exploits specific properties of a recent algorithm.

scholarly journals Building and utilizing fault tolerance support tools for the GASPI applications

2016 ◽  
Vol 32 (5) ◽  
pp. 613-626
Author(s):  
Faisal Shahzad ◽  
Moritz Kreutzer ◽  
Thomas Zeiser ◽  
Rui Machado ◽  
Andreas Pieper ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Fault Detection ◽  
High Performance ◽  
Fault Tolerant ◽  
Low Cost ◽  
Failure Detection ◽  
Detection Mechanism ◽  
Flow Solver ◽  
Recovery Cost ◽  
Recovery Management

Today’s high performance computing systems are made possible by multiple increases in hardware parallelity. This results in the decrease of mean time to failures of the systems with each newer generation, which is an alarming trend. Therefore, it is not surprising that a lot of research is going on in the area of fault tolerance and fault mitigation. Applications should survive a failure and/or be able to recover with minimal cost. We have used Global Address Space Programming Interface (GASPI), which is a relatively new communication library based on the PGAS model. It fulfills the basic requirement of a fault tolerant communication library, i.e. the failure of a process does not cause the remaining processes to fail. This work is focused on extending the fault tolerance features of GASPI in the form of a supporting health-check library that applications can benefit from. These features include failure detection, its information propagation, recovery management, communication recovery, etc. To reinforce its utility, we have also developed a fault tolerant neighbor node-level checkpoint/restart library. Instead of introducing algorithm-based fault tolerance in its true sense, we demonstrate how (using these supplementary fault tolerance functions) one can build applications to allow integrate a low cost fault detection/recovery mechanism and, if necessary, recover the application on the fly. We showcase the usage of these tools by implementing them in three different applications. Two of the applications fall in the category of linear sparse solvers, whereas the third application is based on a fluid flow solver. We also analyze the overheads involved in failure-free cases as well as various failure cases. Our fault detection mechanism causes no overhead in failure-free cases, whereas in case of failure(s), the failure detection and recovery cost is of reasonably acceptable order and shows good scalability.

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