A High-Order Sigma-Delta Modulator Applied in Micro-Accelerometer

2014 ◽  
Vol 609-610 ◽  
pp. 1266-1270
Author(s):  
Jian Yang ◽  
Liang Liu ◽  
Qiu Ye Lv ◽  
Xiao Wei Liu ◽  
Liang Yin
Keyword(s):  
Noise Level ◽  
Signal To Noise Ratio ◽  
High Order ◽  
Signal Frequency ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Ideal Situation ◽  
Micro Accelerometer ◽  
The Ideal

In this paper a high-order sigma-delta modulator applied in micro-accelerometer is designed. The modulator chooses the distributed feedback structure. And the signal bandwidth is 500Hz, the oversampling ratio is 250 and sampling frequency is 250KHz. By the MATLAB Simulink simulation, when the input signal is 1g, and the signal frequency is 250Hz, the simulation result is that the noise level is-160dBV at the signal frequency in the ideal situation. And when considering the non-ideal factors, the simulation result shows that the noise level at the input accelerated signal is 20dBV higher than the ideal. The overall circuit was implemented under 0.5 um CMOS process and simulated in Cadence Spectre. The final simulation results show that the signal to noise ratio (SNR) is 97.1dB.

A 16 Bits Sigma-Delta Modulator Applied in Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 1077-1081
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Ying Kai Zhao ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Cmos Process ◽  
Noise Shaping ◽  
Effective Number ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Multi Stage ◽  
Ideal Situation ◽  
Sample Frequency ◽  
Sigma Delta Adc ◽  
The Ideal

In this paper, a 4th-order sigma-delta modulator applied in gyroscope is presented. This modulator adopts the 2-1-1 Multi stage noise shaping structure. The bandwidth of signal is 100 KHz, the over sample rate is 64, and sample frequency is 12.8MHz. By the MATLAB Simulink modeling and simulation, when the input signal is 100 KHz, the SNDR of the MASH ADC is 121.8dB, and the effective number of bit is 19.93 in ideal situation. After considering non-ideal factors, the SNDR is 111.6dB, the effective number of bit of ADC is 18.28. Compared with the ideal situation, the noise floor of PSD has increased 40dB. It explains that non-ideal factors have a significant effect on the performance of the sigma-delta ADC. The 4th-order MASH sigma-delta modulator has been implemented under 0.5 um CMOS process and simulated under Cadence. The final simulation results show that SNDR is 112.4 dB and effective number of bits (ENOB) is 18.6.

scholarly journals A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4199 ◽  
Author(s):  
Behnam Samadpoor Rikan ◽  
Sang-Yun Kim ◽  
Nabeel Ahmad ◽  
Hamed Abbasizadeh ◽  
Muhammad Riaz Ur Rehman ◽  
...  
Keyword(s):  
Input Signal ◽  
Flicker Noise ◽  
Signal To Noise Ratio ◽  
Pressure Sensors ◽  
High Gain ◽  
Cmos Process ◽  
Signal Conditioning ◽  
Sigma Delta ◽  
Cic Filter ◽  
Decimation Filter

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

1V supply 16-bit second order Sigma-Delta modulator in a 90nm CMOS process

2012 ◽  
Author(s):  
Rochelle Marie F. Amistoso ◽  
Michael Joe A. Bautista ◽  
Rafael Karlo D.P. Delos Santos ◽  
Joana Rochelle R. Ortiz ◽  
Louis P. Alarcon ◽  
...  
Keyword(s):  
Second Order ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Design of a Fourth-Order Sigma-Delta Modulator for Audio Application

2013 ◽  
Vol 380-384 ◽  
pp. 3580-3583
Author(s):  
Ming Yuan Ren ◽  
Tuo Li ◽  
Chang Chun Dong
Keyword(s):  
High Resolution ◽  
Fourth Order ◽  
High Performance ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta

Based on requirements on high performance and high resolution of modulators, a fourth-order Sigma-Delta modulator for audio application is developed in this paper. The modulator is designed under the commercial 0.5μm CMOS process and the circuits are given simulations by Spectre. The sampling frequency of sigma-delta modulator is 11.264 MHz, and OSR is 256 within the 22 kHz signal bandwidth. Measure performance shows that Sigma-Delta modulator enables its maximum SNR to achieve 103.5dB, and the accuracy of Sigma-Delta modulator is up to 16 bit.

scholarly journals A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO

2018 ◽  
Vol 2018 ◽  
pp. 1-8
Author(s):  
Lei Ma ◽  
Na Yan ◽  
Sizheng Chen ◽  
Yangzi Liu ◽  
Hao Min
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Frequency Resolution ◽  
Corner Frequency ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Class C ◽  
Digitally Controlled Oscillator

This paper implements a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start-up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma-delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3 MHz offset from a 5.054 GHz carrier frequency with the 1/f3 corner frequency of 260 KHz. The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A High Bandwidth Sigma-Delta Modulator Applied in Micro-Gyroscope

2013 ◽  
Vol 562-565 ◽  
pp. 369-373 ◽  
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Song Chen ◽  
Peng Fei Wang ◽  
Xiao Wei Liu
Keyword(s):  
Signal To Noise Ratio ◽  
System Simulation ◽  
Sampling Frequency ◽  
Effective Number ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
High Bandwidth ◽  
Oversampling Ratio ◽  
Input Level

In this paper a fourth-order single-loop sigma-delta modulator applied in micro-gyroscope is designed. The modulator system chose the fully feedforword structure. The signal bandwidth is 200KHz, oversampling ratio is 64 and sampling frequency is 25.6MHz. By system simulation result in Matlab, the signal to noise ratio (SNR) is 92.3dB and effective number of bits (ENOB) is 15.03bits. The whole circuit of modulator is designed and simulated in Cadence Spectre. It is gotten that the SNR is 78.6dB and changes linearly with input level. When input level is bigger than -4dBFs, the modulator becomes overload.

Extended use of receiver groups: Theory, synthetic example, and noise considerations

Geophysics ◽  
2020 ◽  
Vol 85 (6) ◽  
pp. P53-P66
Author(s):  
Kjetil E. Haavik
Keyword(s):  
Noise Level ◽  
Signal To Noise Ratio ◽  
Random Noise ◽  
Higher Order ◽  
Sinc Interpolation ◽  
Seismic Acquisition ◽  
Multichannel Sampling ◽  
The Individual ◽  
Derivatives Of ◽  
The Ideal

Receiver grouping is commonly used in marine towed-streamer seismic acquisition. Measurements from several receivers in a group are stacked to increase the signal-to-noise ratio of the resulting data and form an analog spatial antialiasing filter. I propose a method for extracting inline derivatives of the wavefield as additional measurements from the groups. This is achieved by multiplying the signal from the individual receivers in a group with predefined weights that corresponds to a finite-difference (FD) operator. The inline derivative(s) makes it possible to use multichannel sampling theorems to reconstruct the signal on a denser grid. Extraction of FD data from clusters of receivers is not a new concept, but I find that, by using the geometry of conventional streamer groups, it is possible to obtain FD data which are well suited for multichannel interpolation. The key to finding suitable FD operators is to recognize that it is not the ideal differentiation response we seek, but the impulse response of the group multiplied with the ideal differentiation response. Furthermore, under a Gaussian noise assumption, I derive formulas for the resulting noise level from sinc and higher order sinc interpolations. I find that the random noise level in the reconstructed data, when using higher order sinc interpolation, is expected to be higher than when using conventional sinc interpolation and will vary with respect to the distance from the original sampling points. The statistical analysis shows that it is beneficial to find FD operators with as small an [Formula: see text] norm as possible. A synthetic example shows that the proposed method of extracting FD operators and subsequent interpolation works very well. I foresee that the proposed method can be used to reduce the density of receivers (hydrophones or geophones) when designing new streamers or with existing equipment to improve the inline sampling.

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

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