Analysis of the Electron Traps at the 4H-SiC/SiO2 Interface of a Gate Oxide Obtained by Wet Oxidation of a Nitrogen Pre-Implanted Layer

2009 ◽  
Vol 615-617 ◽  
pp. 533-536
Author(s):  
Ioana Pintilie ◽  
Francesco Moscatelli ◽  
Roberta Nipoti ◽  
Antonella Poggi ◽  
Sandro Solmi ◽  
...  
Keyword(s):  
Low Frequency ◽  
Gate Oxide ◽  
High Accuracy ◽  
Interface Trap Density ◽  
Interface Trap ◽  
High Concentration ◽  
Mos Capacitors ◽  
Order Of Magnitude ◽  
Good Agreement

This work is focusing on the effect of a high concentration of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface in MOS capacitors. The N implanted sample (Ninterface ~1x1019cm-3) is compared with a non-implanted one (Ninterface ~1x1016cm-3) by means of the electron interface trap density (Dit). The Dit is determined via High-Low frequency C-V method and Thermal Dielectric Relaxation Current (TDRC) technique. It is shown that the TDRC method, mainly used so far for determination of near interface oxide charges, can be exploited to gain information about the Dit too. The determined value of Dit in the N-implanted sample is nearly one order of magnitude lower than that in the sample without N implantation. Good agreement between the TDRC results and those obtained from High-Low frequency C-V measurements is obtained. Furthermore, the TDRC method shows a high accuracy and resolution of Dit evaluation in the region close to the majority carrier band edge and gives information about the traps located into the oxide.

The Effect of Nitridation on SiC MOS Oxides as Evaluated by Charge Pumping

2008 ◽  
Vol 600-603 ◽  
pp. 743-746 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
J.M. McGarrity ◽  
F. Barry McLean ◽  
Siddharth Potbhare
Keyword(s):  
Gate Oxide ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Interface Traps ◽  
Strong Reduction ◽  
Large Shift ◽  
Mos Capacitors ◽  
Charge Pumping ◽  
Nitridation Process ◽  
Flatband Voltage

We have analyzed the effect of post-oxidation nitride anneals (usually with either NO or N2O gases) on SiC MOSFETs. Two 4H:SiC wafers were identically prepared except that one wafer had a nitridation anneal after the gate oxide was formed, while the other was tested as-oxidized. We compared the two processes by making measurements on lateral MOSFETs and MOS capacitors using ID-VGS, C-V, and charge pumping. There was no change in either flatband voltage or interface trap density near the valence band, suggesting that the net fixed charge remained constant (within a few 1011cm-2). However, there was a large shift in the threshold voltage which, when combined with the C-V results, indicates a strong reduction of interface traps near the conduction band of roughly 6.0x1012cm-2 by using the nitridation process. The charge pumping measurements also showed a strong reduction of interface traps. Charge pumping measured a trapping density of 2.5x1012cm-2 for the as-oxidized samples and 5.3x1011cm-2 for the nitrided samples. The frequency-dependence of the charge pumping signal also indicates a spatial distribution of traps, with volumetric trap densities of roughly 1.3x1019cm-3 over 25Å on as-oxidized and 3.8x1018cm-3 over 19Å for nitrided.

Dependence of the Dielectric Properties of Pt/ZrO2/Si Capacitors Prepared by RF-Magnetron Sputtering on the Oxygen Partial Pressure and the Annealing Temperature

2007 ◽  
Vol 544-545 ◽  
pp. 937-940
Author(s):  
Chong Mu Lee ◽  
Anna Park ◽  
Su Young Park ◽  
Min Woo Park
Keyword(s):  
Magnetron Sputtering ◽  
Annealing Temperature ◽  
Rf Magnetron Sputtering ◽  
Optimum Process ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Flow Ratio ◽  
Mos Capacitors ◽  
Oxide Charge ◽  
Zro2 Film

Effects of the O2/Ar flow ratio in the reactive sputtering process and the annealing temperature on the structure and surface roughness of ZrO2 films and the electric properties of Pt/ZrO2/Si MOS capacitors in which the ZrO2 film was deposited by magnetron sputtering have been investigated. The optimum process parameters of the Pt/ZrO2/Si capacitor based on reactively sputtered- ZrO2 determined in such a way as the capacitance is maximized and the leakage current, the oxide charge, and the interface trap density are minimized is the O2/Ar flow ratio of 1.5 and the annealing temperature of 800°C

Electrical Characterization of GaN Metal Oxide Semiconductor Diode using Sc2O3 as the Gate Oxide

2001 ◽  
Vol 693 ◽  
Author(s):  
R. Mehandru ◽  
B.P. Gila ◽  
J. Kim ◽  
J.W. Johnson ◽  
K.P. Lee ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Inductively Coupled Plasma ◽  
Electron Cyclotron Resonance ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Trap Density ◽  
Oxide Semiconductor ◽  
Semiconductor Diode ◽  
Interface Trap Density ◽  
Interface Trap

AbstractGaN metal oxide semiconductor diodes were demonstrated utilizing Sc2O3 as the gate oxide. Sc2O3 was grown at 100°C on MOCVD grown n-GaN layers in a molecular beam epitaxy (MBE) system, using a scandium elemental source and an Electron Cyclotron Resonance (ECR) oxygen plasma. Ar/Cl2 based discharges was used to remove Sc2O3, in order to expose the underlying n-GaN for ohmic metal deposition in an Inductively Coupled Plasma system. Electron beam deposited Ti/Al/Pt/Au and Pt/Au were utilized as ohmic and gate metallizations, respectively. An interface trap density of 5 × 1011 eV-1cm-2was obtained with the Terman method. Conductance-voltage measurements were also used to estimate the interface trap density and a slightly higher number was obtained as compared to the Terman method. Results of capacitance measurements at elevated temperature (up to 300°C) indicated the presence of deep states near the interface.

Monitoring on Creation and Annihilation of Interface Trap Levels with NO Oxidation, Re-Oxidation and N2 Annealing with Conductance Measurements

2020 ◽  
Vol 1004 ◽  
pp. 595-600
Author(s):  
Xiang Zhou ◽  
Collin W. Hitchcock ◽  
Rajendra P. Dahal ◽  
Gyanesh Pandey ◽  
Jacob Kupernik ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
No Oxidation ◽  
Oxide Semiconductor ◽  
Electron Trapping ◽  
Process Conditions ◽  
Interface Trap ◽  
Annihilation Process ◽  
Mos Capacitors ◽  
Trap Levels

We have determined, using the Conductance-Frequency (G-ω) Technique, the creation and annihilation process of the 3 interface trap levels (OX, OX’ and NI levels) previously reported [1-3] and their possible correlation to inversion electron trapping and mobilities. The measurements were carried out on various 4H-SiC Metal Oxide Semiconductor (MOS) capacitors that have been processed using several gate oxide processes [2,5,6]. Our analysis focus on the correlation of the interface trap levels on the process conditions so as to first understand and then control their formation.

Effect of NH3 Post-Oxidation Annealing on Flatness of SiO2/SiC Interface

2013 ◽  
Vol 740-742 ◽  
pp. 723-726 ◽  
Author(s):  
Narumasa Soejima ◽  
Taishi Kimura ◽  
Tsuyoshi Ishikawa ◽  
Takahide Sugiyama
Keyword(s):  
Nitrous Oxide ◽  
Field Effect ◽  
Inversion Layer ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Field Effect Mobility ◽  
Interfacial Roughness ◽  
Cross Sectional ◽  
Mos Capacitors

We investigated the effects of the post-oxidation annealing (POA) atmosphere on the electrical properties and interfacial roughness of SiO2 deposited on a 4H-SiC (0001) face and SiC. POA in ammonia (NH3) gave MOS capacitors with a lower interface trap density and n-channel MOSFETs with higher field-effect mobility than POA in nitrous oxide (N2O) or nitrogen (N2). In contrast, POA in N2O gave a lower interface trap density than POA in N2, but it gave the lowest field-effect mobility of all the samples. Cross-sectional TEM observations revealed that N2O POA gave a higher interfacial roughness than NH3 POA. We thus considered that N2O POA degraded the inversion-layer mobility due to increased roughness scattering.

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