Analytical Evaluation of Thermally Oxidized and Deposited Dielectric in NMOS-PMOS devices

2016 ◽  
Vol 858 ◽  
pp. 631-634
Author(s):  
Ming Hung Weng ◽  
Muhammad I. Idris ◽  
H.K. Chan ◽  
A.E. Murphy ◽  
D.A. Smith ◽  
...  
Keyword(s):  
Dielectric Film ◽  
Interface State ◽  
State Density ◽  
Mos Capacitors ◽  
High Doping Level ◽  
Channel Mobility ◽  
A Value ◽  
Capacitance Characteristics ◽  
Mos Circuits ◽  
High Temperature Operation

We demonstrate the influence of enhancing the dielectric film used to form the gate in complimentary MOS circuits, designed for high temperature operation. The data show that the characteristics of both n-MOS and p-MOS capacitors and transistors have degraded capacitance characteristics in terms of the trapped charge in the dielectric, although the interface state density is dictated by the underlying stub oxide, at around 5×1012 cm-2eV-1. The use of a deposited oxide also reduces the variability in the critical electric field in the oxide, whilst maintaining a value of approximately 10MV cm-1. The channel mobility extracted from n-and pMOS transistors fabricated alongside the capacitors showed similar values, of approximately 3.8 cm2V-1s-1, which are limited by the high doping level in the epilayers used in this study.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

SiO2/SiC Interface Properties on Various Surface Orientations

2002 ◽  
Vol 742 ◽  
Author(s):  
Hiroshi Yano ◽  
Taichi Hirao ◽  
Tsunenobu Kimoto ◽  
Hiroyuki Matsunami
Keyword(s):  
Conduction Band ◽  
Room Temperature ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Band Edge ◽  
Conduction Band Edge ◽  
Interface Properties ◽  
Mos Capacitors ◽  
Channel Mobility

ABSTRACTThe interface properties of MOS capacitors and MOSFETs were characterized using the (0001), (1120), and (0338) faces of 4H-SiC. (0001) and (1120) correspond to (111) and (110) in cubic structure. (0338) is semi-equivalent to (100). The interface states near the conduction band edge are discussed based on the capacitance and conductance measurements of n-type MOS capacitors at a low temperature and room temperature. The (0338) face indicated the smallest interface state density near the conduction band edge and highest channel mobility in n-channel MOSFETs among these faces.

Effect of Post-Oxidation Annealing in Wet O2 and N2O Ambient on Thermally Grown SiO2/4H-SiC Interface for P-Channel MOS Devices

2012 ◽  
Vol 717-720 ◽  
pp. 709-712 ◽  
Author(s):  
Shuji Katakami ◽  
Manabu Arai ◽  
Kensuke Takenaka ◽  
Yoshiyuki Yonezawa ◽  
Hitoshi Ishimori ◽  
...  
Keyword(s):  
Interfacial Properties ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Promising Method ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Mos Devices ◽  
Inversion Channel ◽  
P Type

We investigated the effect of post-oxidation annealing in wet O2 and N2O ambient, following dry O2 oxidation on the SiC MOS interfacial properties by using p-type MOS capacitors. The interfacial properties were dramatically improved by the introduction of hydrogen or nitrogen atoms into the SiO2/SiC interface, in each POA process. Notably, the N2O-POA process at 1200 °C or higher reduced the interface state density more effectively than the wet-O2-POA process, and offers a promising method to further improve the inversion channel mobility of p-channel SiC MOS devices.

scholarly journals Characterization of SiO2/SiC Interface of Phosphorous-Doped MOS Capacitors by Conductance Measurements

2019 ◽  
Vol 8 (3) ◽  
pp. 5505-5508
Keyword(s):  
Frequency Response ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Conductance Method ◽  
Mos Structures

Interface states of MOS structures capacitors incorporated with low levels of phosphorous have been investigated by conductance and C-ψs method. The frequency response of interface states was observed by the conductance method up to 10 MHz. The correlation between the frequency response of interface states and interface state density determined by C-ψs method was studied. It was found that fast states in phosphorous incorporated samples reduced significantly at high frequency (>5 MHz) while sample annealed with nitrogen remained high up to 10 MHz. The interface state density, Dit of phosphorous incorporated sample near conduction band is lower compared to nitridated sample. These results indicate phosphorous passivation effectively reduces Dit at the SiO2 /SiC interfaces and can be correlated to high channel mobility.

The Correlation between the Reduction of Interface State Density at the SiO2/SiC Interface and the NO Post-Oxide-Annealing Conditions

2019 ◽  
Vol 954 ◽  
pp. 104-108
Author(s):  
Heng Yu Xu ◽  
Cai Ping Wan ◽  
Jin Ping Ao
Keyword(s):  
Mass Spectrometry ◽  
Secondary Ion Mass Spectrometry ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Annealing Conditions ◽  
N Concentration ◽  
Higher Temperature ◽  
Secondary Ion

We fabricated SiO2/4H-SiC (0001) MOS capacitors with oxidation temperature at 1350°C, followed by post-oxide-annealing (POA) in NO simply by the control of POA temperatures and times. A correlation between the reduction of interface state density and the increasing of N concentration at the interface has been indicated by C-ψs measurement and secondary ion mass spectrometry (SIMS). The SiO2/4H-SiC interface density decreased when POA temperature was elevated, and the sample annealed at 1300°C for 30min showed the lowest interface state density about 1.5×1012 cm-2eV-1 at Ec-E=0.3 eV when the N concentration is 11.5×1020 cm-3. Meanwhile, the SiO2 /4H-SiC interface annealed at 1200°C for 120min showed the highest N concentration at the 4H-SiC/SiO2 interface is 12.5×1020 cm-3, whereas the interface state density is 2.5×1012 cm-2eV-1 at Ec-E=0.3 eV higher than 1300°C for 30min. The results suggested that higher temperature POA might be much more efficiency in decreased the 4H-SiC MOS interface density with increasing the N area concentration.

scholarly journals Inversion channel mobility and interface state density of diamond MOSFET using N-type body with various phosphorus concentrations

2019 ◽  
Vol 114 (24) ◽  
pp. 242101 ◽  
Author(s):  
Tsubasa Matsumoto ◽  
Hiromitsu Kato ◽  
Toshiharu Makino ◽  
Masahiko Ogura ◽  
Daisuke Takeuchi ◽  
...  
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Channel Mobility ◽  
Inversion Channel

Effect of Interfacial Localization of Phosphorus on Electrical Properties and Reliability of 4H-SiC MOS Devices

2013 ◽  
Vol 740-742 ◽  
pp. 695-698 ◽  
Author(s):  
Tsuyoshi Akagi ◽  
Hiroshi Yano ◽  
Tomoaki Hatayama ◽  
Takashi Fuyuki
Keyword(s):  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Conduction Band Edge ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Device Properties ◽  
Phosphorus Doped ◽  
Post Deposition ◽  
Mos Device

Metal-oxide-semiconductor (MOS) capacitors with phosphorus localized near the SiO2/SiC interface were fabricated on 4H-SiC by direct POCl3treatment followed by SiO2deposition. Post-deposition annealing (PDA) temperature affected MOS device properties and phosphorus distribution in the oxide. The sample with PDA at 800 °C showed narrow phosphorus-doped oxide region, resulting in low interface state density near the conduction band edge and small flatband voltage shift after FN injection. The interfacial localization of phosphorus improved both interface properties and reliability of 4H-SiC MOS devices.

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

Analysis of Interface Trap Density and Channel Mobility in 4H-SiC NMOS Capacitors and Lateral MOSFETs

2017 ◽  
Vol 897 ◽  
pp. 115-118
Author(s):  
Martin Domeij ◽  
Jimmy Franchi ◽  
Krister Gumaelius ◽  
K. Lee ◽  
Fredrik Allerstam
Keyword(s):  
Threshold Voltage ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Subthreshold Slope ◽  
Gate Oxides ◽  
Channel Mobility

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density DIT for three different gate oxides. DIT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher DIT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and DIT. The subthreshold slope gave similar DIT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.

Sign in / Sign up

Export Citation Format

Share Document