300mm Wafer-Level Image Sensor Packaging

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000699-000716
Author(s):  
Thorsten Matthias ◽  
Bioh Kim ◽  
Gerald Mittendorfer ◽  
Paul Lindner ◽  
Moshe Kriman ◽  
...  
Keyword(s):  
Cost Reduction ◽  
High Volume ◽  
Image Sensor ◽  
Consumer Electronics ◽  
Glass Wafer ◽  
Wafer Level ◽  
Process Technology ◽  
Market Growth ◽  
The Cost ◽  
New Applications

The image sensor market is still showing s tremendous market growth due to applications in consumer electronics, medical, automotive and communication. For a lot of new applications the image sensor packaging is in fact the enabling key technology. The introduction of wafer level packaging a couple of years ago allowed the cost reduction necessary for high volume consumer electronics. Innovative packaging concepts with TSVs and thin dies enable unmatched form factor. Currently scaling image sensor manufacturing and packaging to 300mm is the next big step forward in cost reduction. Wafer level image sensor packaging requires capping of the sensor wafer with a glass wafer. This heterogeneous integration of silicon and glass results in a variety of challenges like thermal expansion mismatch and bow and warp of the wafer stack. In this paper Tessera's OptiML Micro Via Pad technology for image sensors will be described with a special emphasis on equipment and process technology. Wafer encapsulation, via formation, electrical routing, passivation and solder bumping will be discussed.

Fan-Out Packaging: Technologies and market trends

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-35 ◽  
Author(s):  
Jerome Azemar
Keyword(s):  
Cost Reduction ◽  
Business Models ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
High Volume ◽  
Main Trend ◽  
Wafer Level ◽  
Device Scaling ◽  
Application Processor ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level solution aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. In this work we will focus on Fan-Out packaging, an embedded package of most interest at the moment. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature for several years thanks to high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, and with many other developments from OSATs and an aggressive technology from TSMC (inFO). 2016 was a turning point for the Fan-Out market with Apple A1O application processor being packaged using TSMC solution. This partnership changed the game and may create a trend of acceptance of Fan-Out packages for complex applications. The market for Fan-Out packages in 2016 already reached $500M, with potential breakthrough events in store in 2017 that could make the market reach $2B in 2020. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, capable of embedding complex ICs, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC being the first example, foundries too could look at the OSATs reserved market through wafer-level packages, Samsung's reaction being interesting to follow. Each player has its own view on how to gain market share and meet the technical and financial challenges associated to Fan-Out packaging such as cost reduction, yield improvement, die shift… This work brings analysis of the strategies and offers of main players involved and describes potential success scenarios for them. It also helps to define what is Fan-Out Packaging and what are the different products and platforms, player per player, avoiding confusion already visible in the industry where many players call their solution a “Fan-Out” to benefit from the buzz created by Apple despite having significant differences from one to another (chip-first, chip-last, face-up, face-down, etc…). As package price represents the final verdict, carrier size evolution is also an important topic, both for wafers and panels, since it can help to drastically reduce the cost. This work shows that the main trend is still to keep wafer carriers but some players are already investing and developing panel-based solution and we expect volume production soon. While end-customers are pushing for a switch to panel, numerous challenges are limiting its widespread though. This work describes technical, economic and maturity challenges associated to panel manufacturing. Overall, the presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

Ultra-High-Density Interconnect Enabled by Hybrid Bonding for Heterogeneous Integration: Interfacial Characteristics

2021 ◽  
Author(s):  
Mei-Chien Lu
Keyword(s):  
Performance Metrics ◽  
High Volume ◽  
Image Sensor ◽  
Structure Design ◽  
High Density ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Bonding Area ◽  
The Impact ◽  
Interfacial Characteristics

Abstract Hybrid bonding has been explored for more than a decade and implemented recently in high volume production at wafer-to-wafer level for image sensor applications to enable high performance chip-stacking architectures with ultra-high-density chip-to-chip interconnect. The feasibility of sub-micron hybrid bond pitch leading to ultra-high-density chip-to-chip interconnect has been demonstrated due to the elimination of solder bridging issues from microbump method. Hybrid bonding has also been actively considered for logic and memory chip-stacking, chiplets, and heterogeneous integration in general but encountering additional challenges for bonding at die-to-wafer or die-to-die level. Overlay precision, throughput, wafer dicing are among the main causes. Widening the process margin against overlay error by designing innovative hybrid bonding pad structure is highly desirable. This work proposes a method to evaluate these hybrid bonding pad structure designs and to assess the potential performance metrics by analyzing interfacial characteristics at design phase. The bonding areas and ratios of copper-copper, copper-dielectric, and dielectric-dielectric are the proposed key parameters. The correlation between bonding area ratios and overlay errors can provide insights on the sensitivity to process margins. Nonetheless, the impact of copper recess or protrusion associated with bonding area ratios are also highlighted. The proposed method is demonstrated by examining and analyzing the hybrid bonding pad structure design concepts from a few cases reported in literatures as examples. Concerns are identified for elaboration in future designs and optimizations.

Cost Comparison of Panel Level and Wafer Level Fan-out Packaging

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000141-000164
Author(s):  
Amy Lujan
Keyword(s):  
Cost Reduction ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Cost Models ◽  
Wafer Level ◽  
Process Flow ◽  
Total Cost ◽  
Large Panels ◽  
The Cost ◽  
The Impact

In recent years, the possibility of panels replacing wafers in some fan-out applications has been a topic of interest. Questions of cost and yield continue to arise even as the industry appears to be full steam ahead. While large panels allow for more packages to be produced at once, the cost does not scale simply based on how many more packages can be generated from a panel over a wafer. This analysis begins by breaking down the types of cost and will discuss how those types of cost are impacted (or not) by the shift from wafer to panel. Activity based cost modeling is used; this is a detailed, bottom-up approach that takes into account each type of cost for each activity in a process flow. Two complete cost models were constructed for this analysis. A variety of package sizes are analyzed, and multiple panel sizes are included as well. For each set of activities in the fan-out process flow, there is an explanation of how the process changes with the move to panel, including assumptions related to throughput, equipment price, and materials. The cost reduction that may be achieved at each package and panel size will be presented for each processing segment. The focus of this analysis is on the details of each segment of the process flow, but results for the total cost of various packages will also be presented. There is also a section of analysis related to the impact of yield on the competitiveness of panel processing.

Cost Analysis of TSV Process and Scaling Options

2014 ◽  
Vol 2014 (1) ◽  
pp. 000001-000007
Author(s):  
Victor Vartanian ◽  
Larry Smith ◽  
Klaus Hummler ◽  
Steve Olson ◽  
Brian Sapp ◽  
...  
Keyword(s):  
High Volume ◽  
Film Structure ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Factors Affecting ◽  
Multiple Process ◽  
Cost Of Materials ◽  
The Cost ◽  
The Impact ◽  
Cost Differences

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm. These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable. We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions. The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal.

Solutions for Wafer-Level Packaging of High Brightness LEDs

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001418-001442
Author(s):  
Thomas Uhrmann ◽  
B. Kim ◽  
T. Matthias ◽  
P. Lindner
Keyword(s):  
Form Factor ◽  
Light Output ◽  
High Volume ◽  
Performance Ratio ◽  
High Yield ◽  
Light Sources ◽  
Wafer Level ◽  
Process Step ◽  
High Brightness ◽  
The Cost

High brightness LEDs (HB-LEDs) carry a high prospect for general lighting applications. Competing with the cost/performance ratio of current light sources demands an increase of the overall efficiency as well as the reduction of the device cost. Since packaging accounts for 30%–50% of the cost of HB LED manufacturing, moving from die- level to wafer-level processes is one likely potential solution for reducing cost per lumen. Silicon-based WLP, using the established processing technology of the MEMS and IC industry, offers high fabrication reliability, high yield and the direct integration of the driver IC in the package. The already small form factor of WLP can be further reduced using Through-Silicon-Vias (TSV), increasing the maximum amount of chips per wafer. Silicon WLP also offers superior thermal management, with the relatively high thermal conductance of silicon. Redistributing LED dies on silicon wafer submounts, with metal bonding and copper TSVs, further improves the heat conductance away from the active region of the chip, resulting in increased device performance. Wafer-level optics can further improve performance and reduce packaging costs. Wafer-level lens molding based on imprint lithography is in high volume manufacture for cell phone camera modules. It allows creation of spherical and a-spherical lenses as well as lens stacks with minimized form factor. In contrast to the currently applied drop dispensing technique for LED lens fabrication, the shape of the lens can be accurately tailored and the decrease of the lens size results in lower absorption and higher light output. Most of these technologies are already in high volume production in other sectors. We will discuss the field proven solutions at each process step, from the formation of the silicon interposer, through the chip-to-wafer bonding, to the final imprinting of the wafer-level optics.

Chip Last Fan Out as an Alternative to Chip First

2015 ◽  
Vol 2015 (1) ◽  
pp. 000245-000250 ◽  
Author(s):  
Scott Chen ◽  
Simon Wang ◽  
Coltrane Lee ◽  
Adren Hsieh ◽  
John Hunt ◽  
...  
Keyword(s):  
Low Cost ◽  
Smart Phone ◽  
High Volume ◽  
Smart Phones ◽  
Portable Devices ◽  
Wafer Level ◽  
Packaging Technology ◽  
Two Factors ◽  
The Cost ◽  
Technology Nodes

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, and they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), and system in package (SIP) being widely used in these smart phones & mobile devices.. Fan out WLCSP (FOWLP) has great potential to be the next new package for the smart phone mobility application. Two factors have driven fan out WLCSP (FOWLP) package technology in the last few years. The first is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solder ball interconnects. The second and potentially more important factor relates to the demand of the market for more functions. Not all silicon functionality benefits from these advanced nodes, and merely adds to the cost of the die. This has driven the designers to partitioning of desired functionality into multiple die, which in turn requires effective interconnection of these separate die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). Up to date FOWLP used chip first processing, in which the bare die was molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a new alternative to chip first FOWLP, an alternative which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package has been in production in ASE for over a year, and uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented. We have designated this package structure “Fan Out Chip Last Package (FOCLP)” For higher end applications we will show the ability to use a high density substrate process for use in more demanding chip last fan out packages

Adhesive Strength Characterization of CYTOP™: Low Temperature Wafer-Level Packaging

2006 ◽  
Author(s):  
Vikram Patil ◽  
Chad B. O'Neal
Keyword(s):  
Bond Strength ◽  
Adhesive Bonding ◽  
High Volume ◽  
Micro Electro Mechanical System ◽  
Curing Temperature ◽  
Temperature Sensitive ◽  
Glass Wafer ◽  
Mems Devices ◽  
Wafer Level ◽  
Strength Characterization

This study describes a wafer bonding technique using CYTOP™ inking method for the high volume packaging of micro-electro mechanical system (MEMS) devices. CYTOP™ is a class of perfluoro (alkenyl vinyl ether) polymer which is obtained by cyclopolymerization of perfluoro. The CYTOP™ adhesive bonding requires much lower temperature (150 to 200° C) compared to other bonding techniques such as soldering (> 250° C) or anodic (~350° C) bonding. The lower temperatures involved in the process reduce the risk of thermal damage to temperature sensitive devices during packaging. The described bonding process consists of a wet inking technique in which wet CYTOP™ ink is applied on soft cured CYTOP™ before bonding. In this study, CYTOP™ is characterized for its bonding strength and quality. The experiments are performed on silicon and glass wafer substrates. The bonded samples are pull-tested and tensile stress values are recorded at the instance of bond failure. About 90% of the samples failed at the bonding interface which indicates that the recorded stress values are the bond strength of CYTOP™. The bond strength of CYTOP™ depends upon the curing temperature and the curing time. The highest bond strength of 16. 46 MPa is recorded at 200° C and 45 min. of curing. The CYTOP™ bond strength at 200° C is comparable with bond strength of BCB at 250° C.

Low Cost Chip Last Fanout Package using Coreless Substrate

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000272-000300 ◽  
Author(s):  
Scott Chen ◽  
Simon Wang ◽  
Coltrane Lee ◽  
John Hunt
Keyword(s):  
Low Cost ◽  
Single Layer ◽  
High Volume ◽  
Smart Phones ◽  
Portable Devices ◽  
Wafer Level ◽  
Packaging Technology ◽  
Two Factors ◽  
The Cost ◽  
Technology Nodes

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, but at the same time they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) being widely used in these smart phones & mobile devices. Two factors have driven a new package technology within the last 10 years. One is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solderball interconnects. The second factor also relates to the advancing technology nodes. Not all silicon functionality benefits from there advanced nodes, and merely adds to the cost of the die. This has driven the partitioning of device functionality into multiple die, which in turn requires effective interconnection of these partitioned die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). The typical FOWLP uses chip first processing, in which the bare die is molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a relatively low cost alternative to FOWLP, which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. All previous FOWLP designs at ASE were able to be routed in a single layer using this new packaging technology . Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented.

Advances in Wafer Level Processing and Integration for CIS Module Manufacturing

2010 ◽  
Vol 2010 (1) ◽  
pp. 000378-000384
Author(s):  
Bioh Kim ◽  
Thorsten Matthias ◽  
Gerald Kreindl ◽  
Viorel Dragoi ◽  
Markus Wimplinger ◽  
...  
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Volume ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Handheld Devices ◽  
Wafer Level ◽  
Sensor Module ◽  
Integration Techniques ◽  
Backside Illuminated

This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.

Fan-Out Wafer-Level-Packaging: Market and Technology Trends

2016 ◽  
Vol 2016 (1) ◽  
pp. 000176-000179 ◽  
Author(s):  
Jérôme Azémar
Keyword(s):  
Cost Reduction ◽  
Flip Chip ◽  
Business Models ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
High Volume ◽  
Added Value ◽  
System Level ◽  
Wafer Level ◽  
High Expectations

Abstract The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D/3D IC solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. Embedded packages are nowadays not anymore just an interesting approach for specific applications. Benefiting from 3D TSV high cost, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players, lately most notably TSMC. In this work we will focus on one main type of embedded package of most interest at the moment: Fan-Out wafer level package. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, with many other developments from OSATs and an aggressive technology from TSMC (inFO). The market for Fan-Out packages in 2015 almost reached $500M, with potential breakthrough events in store in 2016 that could triple the 2015 market and continue further with more than 30% growth. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

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