Ultra-High-Density Interconnect Enabled by Hybrid Bonding for Heterogeneous Integration: Interfacial Characteristics

2021 ◽  
Author(s):  
Mei-Chien Lu
Keyword(s):  
Performance Metrics ◽  
High Volume ◽  
Image Sensor ◽  
Structure Design ◽  
High Density ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Bonding Area ◽  
The Impact ◽  
Interfacial Characteristics

Abstract Hybrid bonding has been explored for more than a decade and implemented recently in high volume production at wafer-to-wafer level for image sensor applications to enable high performance chip-stacking architectures with ultra-high-density chip-to-chip interconnect. The feasibility of sub-micron hybrid bond pitch leading to ultra-high-density chip-to-chip interconnect has been demonstrated due to the elimination of solder bridging issues from microbump method. Hybrid bonding has also been actively considered for logic and memory chip-stacking, chiplets, and heterogeneous integration in general but encountering additional challenges for bonding at die-to-wafer or die-to-die level. Overlay precision, throughput, wafer dicing are among the main causes. Widening the process margin against overlay error by designing innovative hybrid bonding pad structure is highly desirable. This work proposes a method to evaluate these hybrid bonding pad structure designs and to assess the potential performance metrics by analyzing interfacial characteristics at design phase. The bonding areas and ratios of copper-copper, copper-dielectric, and dielectric-dielectric are the proposed key parameters. The correlation between bonding area ratios and overlay errors can provide insights on the sensitivity to process margins. Nonetheless, the impact of copper recess or protrusion associated with bonding area ratios are also highlighted. The proposed method is demonstrated by examining and analyzing the hybrid bonding pad structure design concepts from a few cases reported in literatures as examples. Concerns are identified for elaboration in future designs and optimizations.

SYSTEMATIC FEEDBACK LOOP FOR SILICON DIE PICK&PLACE PROCESS IN RECONSTITUTED FAN-OUT EWLB WAFERS IN HIGH VOLUME PRODUCTION

2012 ◽  
Vol 2012 (1) ◽  
pp. 000201-000208 ◽  
Author(s):  
Alberto Martins ◽  
Nelson Pinho ◽  
Harald Meixner
Keyword(s):  
Feedback Loop ◽  
High Volume ◽  
Data Availability ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Wafer Thickness ◽  
High Volume Production ◽  
Cte Mismatch ◽  
Volume Production ◽  
The Impact

NANIUM S.A. Portugal recently started producing eWLB fan-out [1][2] wafer level packaging technology on 300mm reconstituted wafers. Initial setup of this process demonstrated that the stable die Pick&Place accuracy plays a key role for product feasibility. In the subsequent volume production ramp-up it became apparent that the dynamic expansion of molded eWLB wafers, caused by thermal stress and CTE mismatch throughout the thin film redistribution and passivation layer up to bumping and reflow manufacturing processes requires a very tight die position monitoring over the complete wafer diameter. Feedback loop to the initial die placement and implementation of correction measures is essential to meet the quality and yield targets of different product configurations (die sizes, distance between dies, die thickness, wafer thickness, single die or system-inpackage) in high volume manufacturing. Stability and repeatability is of outermost importance. The paper will discuss the effects seen on the wafer, the monitoring and the strategies for feedback loop process enabling implementation of corrections into the reconstituted wafer before forming the artificial backend wafer by compression molding. The setup of adequate metrology steps throughout the process line supports the control of the various interlayer alignments. The end result is a centered process in the initial Pick&Place and various subsequent lithography steps (Stepper and Mask Aligner). Sustained data availability and processed data visualization made possible the development of an elaborate theoretical model enabling systematic optimizations of machine parameters and material expansion/compression correction factors. The model also permits the immediate visualization of the impact of each machine parameter on the global result.

Assembly Equipment Requirements for Next Generation Advanced Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann
Keyword(s):  
Capital Investment ◽  
Flip Chip ◽  
High Volume ◽  
Electrical Performance ◽  
Wafer Level ◽  
Considerable Uncertainty ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
The Impact ◽  
3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

300mm Wafer-Level Image Sensor Packaging

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000699-000716
Author(s):  
Thorsten Matthias ◽  
Bioh Kim ◽  
Gerald Mittendorfer ◽  
Paul Lindner ◽  
Moshe Kriman ◽  
...  
Keyword(s):  
Cost Reduction ◽  
High Volume ◽  
Image Sensor ◽  
Consumer Electronics ◽  
Glass Wafer ◽  
Wafer Level ◽  
Process Technology ◽  
Market Growth ◽  
The Cost ◽  
New Applications

The image sensor market is still showing s tremendous market growth due to applications in consumer electronics, medical, automotive and communication. For a lot of new applications the image sensor packaging is in fact the enabling key technology. The introduction of wafer level packaging a couple of years ago allowed the cost reduction necessary for high volume consumer electronics. Innovative packaging concepts with TSVs and thin dies enable unmatched form factor. Currently scaling image sensor manufacturing and packaging to 300mm is the next big step forward in cost reduction. Wafer level image sensor packaging requires capping of the sensor wafer with a glass wafer. This heterogeneous integration of silicon and glass results in a variety of challenges like thermal expansion mismatch and bow and warp of the wafer stack. In this paper Tessera's OptiML Micro Via Pad technology for image sensors will be described with a special emphasis on equipment and process technology. Wafer encapsulation, via formation, electrical routing, passivation and solder bumping will be discussed.

Cost Analysis of TSV Process and Scaling Options

2014 ◽  
Vol 2014 (1) ◽  
pp. 000001-000007
Author(s):  
Victor Vartanian ◽  
Larry Smith ◽  
Klaus Hummler ◽  
Steve Olson ◽  
Brian Sapp ◽  
...  
Keyword(s):  
High Volume ◽  
Film Structure ◽  
Manufacturing Cost ◽  
Wafer Level ◽  
Factors Affecting ◽  
Multiple Process ◽  
Cost Of Materials ◽  
The Cost ◽  
The Impact ◽  
Cost Differences

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm. These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable. We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions. The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal.

Advances in Wafer Level Processing and Integration for CIS Module Manufacturing

2010 ◽  
Vol 2010 (1) ◽  
pp. 000378-000384
Author(s):  
Bioh Kim ◽  
Thorsten Matthias ◽  
Gerald Kreindl ◽  
Viorel Dragoi ◽  
Markus Wimplinger ◽  
...  
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Volume ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Handheld Devices ◽  
Wafer Level ◽  
Sensor Module ◽  
Integration Techniques ◽  
Backside Illuminated

This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.

Development of Wafer Level Chip Size Packaging Process and its Application to the CMOS Image Sensor Module for Medical Device

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  
Keyword(s):  
Medical Device ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wafer Level ◽  
Packaging Process ◽  
Sensor Module ◽  
Chip Size

Evaluation of the Aging Behavior of High Density Polyethylene in Thermal Oxidative Environment by Principal Component Analysis

2017 ◽  
Vol 727 ◽  
pp. 447-449 ◽  
Author(s):  
Jun Dai ◽  
Hua Yan ◽  
Jian Jian Yang ◽  
Jun Jun Guo
Keyword(s):  
Principal Component Analysis ◽  
Impact Strength ◽  
High Density Polyethylene ◽  
Tensile Modulus ◽  
Principal Component ◽  
Component Analysis ◽  
High Density ◽  
Aging Behavior ◽  
Data Set ◽  
The Impact

To evaluate the aging behavior of high density polyethylene (HDPE) under an artificial accelerated environment, principal component analysis (PCA) was used to establish a non-dimensional expression Z from a data set of multiple degradation parameters of HDPE. In this study, HDPE samples were exposed to the accelerated thermal oxidative environment for different time intervals up to 64 days. The results showed that the combined evaluating parameter Z was characterized by three-stage changes. The combined evaluating parameter Z increased quickly in the first 16 days of exposure and then leveled off. After 40 days, it began to increase again. Among the 10 degradation parameters, branching degree, carbonyl index and hydroxyl index are strongly associated. The tensile modulus is highly correlated with the impact strength. The tensile strength, tensile modulus and impact strength are negatively correlated with the crystallinity.

scholarly journals Development and Prospect of UAV-Based Aerial Electrostatic Spray Technology in China

2021 ◽  
Vol 11 (9) ◽  
pp. 4071
Author(s):  
Yali Zhang ◽  
Xinrong Huang ◽  
Yubin Lan ◽  
Linlin Wang ◽  
Xiaoyang Lu ◽  
...  
Keyword(s):  
Plant Protection ◽  
Structure Design ◽  
Research Progress ◽  
Theoretical Simulation ◽  
Spray System ◽  
Charged Droplets ◽  
Agricultural Use ◽  
Field Efficiency ◽  
The Impact ◽  
Electrostatic Spray

Aerial electrostatic spray technology for agriculture is the integration of precision agricultural aviation and electrostatic spray technology. It is one of the research topics that have been paid close attention to by scholars in the field of agricultural aviation. This study summarizes the development of airborne electrostatic spray technology for agricultural use in China, including the early research and exploration of Chinese institutions and researchers in the aspects of nozzle structure design optimization and theoretical simulation. The research progress of UAV-based aerial electrostatic spray technology for agricultural use in China was expounded from the aspects of nozzle modification, technical feasibility study, influencing mechanism of various factors, and field efficiency tests. According to the current development of agricultural UAVs and the characteristics of the farmland environment in China, the UAV-based aerial electrostatic spray technology, which carries the airborne electrostatic spray system on the plant protection UAVs, has a wide potential in the future. At present, the application of UAV-based aerial electrostatic spray technology has yet to be further improved due to several factors, such as the optimization of the test technology for charged droplets, the impact of UAV rotor wind field, comparison study on charging modes, and the lack of technical accumulation in the research of aerial electrostatic spray technology. With the continuous improvement of the research system of agricultural aviation electrostatic spray technology, UAV-based electrostatic spray technology will give play to the advantages in increasing the droplets deposition on the target and reducing environmental pollution from the application of pesticides. This study is capable of providing a reference for the development of the UAV-based agricultural electrostatic spray technology and the spray equipment.

scholarly journals Kinematics and dynamics analysis of new rotary-percussive PDM drilling tool

2021 ◽  
pp. 146134842198915
Author(s):  
Jialin Tian ◽  
Xuehua Hu ◽  
Liming Dai ◽  
Lin Yang ◽  
Yi Yang ◽  
...  
Keyword(s):  
Drill String ◽  
Structure Design ◽  
Drilling Process ◽  
Analysis Model ◽  
Drilling Tool ◽  
Stick Slip ◽  
Rate Of Penetration ◽  
Bottom Hole ◽  
Bottom Hole Assembly ◽  
The Impact

This paper presents a new drilling tool with multidirectional and controllable vibrations for enhancing the drilling rate of penetration and reducing the wellbore friction in complex well structure. Based on the structure design, the working mechanism is analyzed in downhole conditions. Then, combined with the impact theory and the drilling process, the theoretical models including the various impact forces are established. Also, to study the downhole performance, the bottom hole assembly dynamics characteristics in new condition are discussed. Moreover, to study the influence of key parameters on the impact force, the parabolic effect of the tool and the rebound of the drill string were considered, and the kinematics and mechanical properties of the new tool under working conditions were calculated. For the importance of the roller as a vibration generator, the displacement trajectory of the roller under different rotating speed and weight on bit was compared and analyzed. The reliable and accuracy of the theoretical model were verified by comparing the calculation results and experimental test results. The results show that the new design can produce a continuous and stable periodic impact. By adjusting the design parameter matching to the working condition, the bottom hole assembly with the new tool can improve the rate of penetration and reduce the wellbore friction or drilling stick-slip with benign vibration. The analysis model can also be used for a similar method or design just by changing the relative parameters. The research and results can provide references for enhancing drilling efficiency and safe production.

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