Fan-Out Wafer-Level-Packaging: Market and Technology Trends

Abstract The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D/3D IC solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. Embedded packages are nowadays not anymore just an interesting approach for specific applications. Benefiting from 3D TSV high cost, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players, lately most notably TSMC. In this work we will focus on one main type of embedded package of most interest at the moment: Fan-Out wafer level package. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, with many other developments from OSATs and an aggressive technology from TSMC (inFO). The market for Fan-Out packages in 2015 almost reached $500M, with potential breakthrough events in store in 2016 that could triple the 2015 market and continue further with more than 30% growth. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

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Fan-Out Packaging: Technologies and market trends

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2017dpc-ta2_presentation1 ◽

2017 ◽

Vol 2017 (DPC) ◽

pp. 1-35 ◽

Cited By ~ 3

Author(s):

Jerome Azemar

Keyword(s):

Cost Reduction ◽

Business Models ◽

Semiconductor Industry ◽

Cost Benefit ◽

High Volume ◽

Main Trend ◽

Wafer Level ◽

Device Scaling ◽

Application Processor ◽

The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level solution aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. In this work we will focus on Fan-Out packaging, an embedded package of most interest at the moment. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature for several years thanks to high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, and with many other developments from OSATs and an aggressive technology from TSMC (inFO). 2016 was a turning point for the Fan-Out market with Apple A1O application processor being packaged using TSMC solution. This partnership changed the game and may create a trend of acceptance of Fan-Out packages for complex applications. The market for Fan-Out packages in 2016 already reached $500M, with potential breakthrough events in store in 2017 that could make the market reach $2B in 2020. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, capable of embedding complex ICs, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC being the first example, foundries too could look at the OSATs reserved market through wafer-level packages, Samsung's reaction being interesting to follow. Each player has its own view on how to gain market share and meet the technical and financial challenges associated to Fan-Out packaging such as cost reduction, yield improvement, die shift… This work brings analysis of the strategies and offers of main players involved and describes potential success scenarios for them. It also helps to define what is Fan-Out Packaging and what are the different products and platforms, player per player, avoiding confusion already visible in the industry where many players call their solution a “Fan-Out” to benefit from the buzz created by Apple despite having significant differences from one to another (chip-first, chip-last, face-up, face-down, etc…). As package price represents the final verdict, carrier size evolution is also an important topic, both for wafers and panels, since it can help to drastically reduce the cost. This work shows that the main trend is still to keep wafer carriers but some players are already investing and developing panel-based solution and we expect volume production soon. While end-customers are pushing for a switch to panel, numerous challenges are limiting its widespread though. This work describes technical, economic and maturity challenges associated to panel manufacturing. Overall, the presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

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Embedded solutions: Fan-out and Embedded Die Packages market and technology trends

International Symposium on Microelectronics ◽

10.4071/isom-2015-wa31 ◽

2015 ◽

Vol 2015 (1) ◽

pp. 000235-000238

Author(s):

Jérôme Azémar

Keyword(s):

Supply Chain ◽

Business Models ◽

Low Cost ◽

High Volume ◽

Added Value ◽

System Level ◽

Wafer Level ◽

High Expectations ◽

Interesting Approach ◽

Pcb Manufacturing

Embedded packages are nowadays not anymore just an interesting approach for some specific application. Benefiting from 3D TSV high cost, and consequently delays, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players. In this presentation we will focus on two main types of embedded packages, those that are most of interest at the moment: Fan-Out and Embedded Dies packages. The principle of Fan Out technology is to embed products in a molded compound and allow redistribution layers pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and Stats ChipPAC using eWLB type of Fan-Out. Market for Fan-Out packages in 2014 almost reached $200M and a 20% growth for the coming years is expected. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like SPIL or J-Devices are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The principle of Embedded die packages has the same purpose of promoting high integration due to placing chips within the substrate but with a different approach: Embedding is done in laminate substrates. This process is pushed by PCB manufacturers such as AT&S and could create a new supply chain with new players. One of the main advantages is to use a mature and cheap manufacturing chain created for PCB manufacturing and then having low cost for a technology that would allow a good integration and access to both sides of the chips easily. On the other hand, Embedded Die technologies are still waiting for a high volume project that shall be coming once higher yield, better resolution and clarification of the supply chain will be achieved. In this presentation we will describe what the strategies to reach that goal are. Both technologies seem to be competing but are actually complementary and often targeting different markets. Key customers already qualified them and will open the gates for the fast growing packaging market. The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out and embedded die packaging approaches by applications, business models and major players will be reviewed.

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Embedded solutions: Fan-out and Embedded Dies Packages market and technology trends

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2015dpc-ta21 ◽

2015 ◽

Vol 2015 (DPC) ◽

pp. 000182-000216 ◽

Cited By ~ 1

Author(s):

Jerome AZEMAR ◽

Rozalia BEICA ◽

Thibault BUISSON ◽

Andrej IVANCOVIC ◽

Amandine PIZZAGALLI

Keyword(s):

Supply Chain ◽

Business Models ◽

Low Cost ◽

High Volume ◽

Added Value ◽

System Level ◽

Wafer Level ◽

High Expectations ◽

Interesting Approach ◽

Pcb Manufacturing

Embedded packages are nowadays not anymore just an interesting approach for some specific application. Benefiting from 3D TSV high cost, and consequently delays, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players. In this presentation we will focus on two main types of embedded packages, those that are most of interest at the moment: Fan-Out and Embedded Dies packages. The principle of Fan Out technology is to embed products in a molded compound and allow redistribution layers pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and Stats ChipPAC using eWLB type of Fan-Out. Market for Fan-Out packages in 2014 almost reached $200M and a 20% growth for the coming years is expected. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like SPIL or J-Devices are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The principle of Embedded dies package has the same purpose of promoting high integration due to placing chips within the substrate but with a different approach: Embedding is done in laminate substrates. This process is pushed by PCB manufacturers such as AT&S and could create a new supply chain with new players. One of the main advantages is to use a mature and cheap manufacturing chain created for PCB manufacturing and then having low cost for a technology that would allow a good integration and access to both sides of the chips easily. On the other hand, Embedded Die technologies are still waiting for a high volume project that shall be coming once higher yield, better resolution and clarification of the supply chain will be achieved. In this presentation we will describe what the strategies to reach that goal are. Both technologies seem to be competing but are actually complementary and often targeting different markets. Key customers already qualified them and will open the gates for the fast growing packaging market. The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out and embedded die packaging approaches by applications, business models and major players will be reviewed.

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Fan-in WLP: Technology and Market Trends

International Symposium on Microelectronics ◽

10.4071/isom-2015-tp31 ◽

2015 ◽

Vol 2015 (1) ◽

pp. 000067-000072 ◽

Cited By ~ 3

Author(s):

A. Ivankovic ◽

T. Buisson ◽

S. Kumar ◽

A. Pizzagalli ◽

J. Azemar ◽

...

Keyword(s):

Flip Chip ◽

Semiconductor Industry ◽

Cost Benefit ◽

Current Status ◽

Wafer Level ◽

New Era ◽

Device Scaling ◽

Depth Analysis ◽

Application Diversification ◽

The Cost

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Electroplating with Dielectric Bridges

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2015dpc-tp22 ◽

2015 ◽

Vol 2015 (DPC) ◽

pp. 000590-000610

Author(s):

Gene Stout ◽

Doug Scott ◽

Anthony Curtis ◽

Guy Burgess ◽

Theodore G. Tessier

Keyword(s):

Seed Layer ◽

Flip Chip ◽

Semiconductor Industry ◽

High Volume ◽

Wafer Level ◽

Semiconductor Wafer ◽

Front End ◽

Dielectric Layers ◽

Alternative Means ◽

Assembly Operations

The electroplating of underlying metal redistribution layers, under-bump metallization (UBM) layers, WLCSP, Cu pillar and other flip chip applications is well established in the semiconductor industry. The use of semi-additive plating can sometimes be adversely affected by the absence of plating occurring in all targeted locations or with plating non-uniformity as a result of front-end fab related structural anomalies. Subsequent analysis has routinely determined that the previously deposited metal seed layer had been discontinuous due to the topography of wafer features. The most predominant types of topographical issues causing discontinuity in the seed layer are related to adverse sidewall profiles of an underlying dielectric layer or an edge of die feature. Typically die streets are kept clear of certain dielectric layers to avoid complications from saw tool wear and residual defects. As such, these particular dielectric layers are usually terminated at or near each die edge on a semiconductor wafer during processing. Introducing dielectric bridges over the dicing streets provides additional assurances an alternative means to significantly improve the ability to uniformly plate on all targeted die by creating an electrically continuous seed layer pathway while still allowing for subsequent wafer dicing with minimal blade wear, die chipping or residual dielectric issues. FCI has developed and successfully uses this patent pending method to insure the uniform electroplating of metallization layers for a wide variety of applications. This paper will highlight the advantages of this wafer level processing strategy in a high volume, high mix wafer bump fabrication facility including improvements in processing quality and consistency. The transparency on deploying this front-end process change on back-end assembly operations and device reliability will also be addressed.

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Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices”

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2380-4491-2019-dpc-presentation_tp1_073 ◽

2019 ◽

Vol 2019 (DPC) ◽

pp. 000383-000407

Author(s):

Kevin Moody ◽

Nick Stukan

Keyword(s):

Supply Chain ◽

Business Models ◽

High Reliability ◽

Semiconductor Industry ◽

Thermal Dissipation ◽

System Level ◽

Electrical Performance ◽

Power Devices ◽

Embedded Technology ◽

New Device

In this paper will focus on the comprehension of System-in-Package (SiP) with embedded active and passive components integration will be described. Embedding of semiconductor chips into substrates provides many advantages that have been noted. It allows the smallest package form-factor with high degree of miniaturization through sequentially stacking of multiple layers containing embedded devices that are optimized for electrical performance with short and geometrically well controlled copper interconnects. In addition, the embedding gives a homogeneous mechanical environment of the chips, resulting in good reliability at system level. Furthermore, embedded technology is an excellent resolution to Power management challenges dealing with new device technologies (Si, GaS, GaN) and optimization on the thermal dissipation with improved efficiency. Embedded technology comes with many challenges in 2019, primarily design for manufacturability (DFM) and maturity. Customers are looking for better-performance capability and pricing normally that means same or lower than die free package cost (DFPC) comparison. This paper will discuss the challenges bring to market the Embedded SIP Modules for next-GEN Heterogeneous “POWER-Devices” Today, the embedded process is being developed by printed circuit board (PCB) manufacturers creating a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models. As a result of the increasing interest in implementing embedding technologies, ACCESS Semiconductors in China is committed to be a leader in the adaptation of embedding technologies, with over 10-yrs mature coreless technology and proved design rules for low profile dimensions with seamless Ti/Cu sputtering and Cu pillar interconnect giving advantages in both electrical & power performance. ACCESS Patented “Via-in-Frame” technology provides High Reliability (MSL1, PCT, BHAST) at Cost Effective in high panel utilization for HVM, using standard substrate/PCB known material sets, no need for wafer bumping/RDL, over-mold or under-fill cost adders. ACCESS Semiconductors is currently in HVM on single die 2L, and LVM on multi-devices actives/passives 4L SiP construction both platforms are driven from the power market segment. In-development on Die Last & Frameless (MeSiP) platforms utilizing hybrid technology (mSAP) and Photo Imageable Dielectric (PID) materials for cost down solutions in HVM by Q1FY2020. Also, ACCESS Semiconductors total turn-key solutions will include front-of-line (FOL) and end-of-line (EOL) capability from wafer handling, back-grinding, and dicing with KGD traceability thru the embedded chip process, frame/strip singulation, FT, marking pack & ship providing additional 30% cost reduction in the future. Here's an illustration of Embedded Technology Roadmap and Product Platforms.

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3D Technology Applications Market Trends & Key Challenges

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2014pdc/ta11 ◽

2014 ◽

Vol 2014 (DPC) ◽

pp. 000363-000400

Author(s):

Thibault Buisson ◽

Amandine Pizzagalli ◽

Eric Mounier ◽

Rozalia Beica

Keyword(s):

Supply Chain ◽

Business Models ◽

Semiconductor Industry ◽

High Volume ◽

Advanced Technology ◽

Passive Component ◽

Process Technology ◽

3D Integration ◽

3D Technology ◽

Major Player

Semiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging option, considered today the most advanced technology, that could enable various heterogeneous integration. Indeed such technology is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive component...) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that need to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers & 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with a multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

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Creating Semiconductor Value through Advanced Package Technology

International Symposium on Microelectronics ◽

10.4071/isom-2016-slide-1 ◽

2016 ◽

Vol 2016 (S1) ◽

pp. S1-S46

Author(s):

Ron Huemoeller

Keyword(s):

Big Five ◽

Flip Chip ◽

Microelectromechanical Systems ◽

Technology Innovation ◽

Low Cost ◽

Semiconductor Industry ◽

Significant Shift ◽

Wafer Level ◽

Chip Scale Package ◽

Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

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Assembly Equipment Requirements for Next Generation Advanced Packaging

International Symposium on Microelectronics ◽

10.4071/isom-2016-wp35 ◽

2016 ◽

Vol 2016 (1) ◽

pp. 000321-000325

Author(s):

Bob Chylak ◽

Horst Clauberg ◽

Tom Strothmann

Keyword(s):

Capital Investment ◽

Flip Chip ◽

High Volume ◽

Electrical Performance ◽

Wafer Level ◽

Considerable Uncertainty ◽

Thermocompression Bonding ◽

Advanced Packaging ◽

The Impact ◽

3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

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A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

Journal of Electronic Packaging ◽

10.1115/1.2804096 ◽

2007 ◽

Vol 129 (4) ◽

pp. 460-468 ◽

Cited By ~ 7

Author(s):

Karan Kacker ◽

Thomas Sokol ◽

Wansuk Yun ◽

Madhavan Swaminathan ◽

Suresh K. Sitaraman

Keyword(s):

Flip Chip ◽

Dielectric Material ◽

Coefficient Of Thermal Expansion ◽

Semiconductor Industry ◽

Organic Substrate ◽

Electrical Performance ◽

Integrative Approach ◽

Wafer Level ◽

Target Values ◽

Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

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