Fan-Out Packaging: Technologies and market trends

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level solution aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. In this work we will focus on Fan-Out packaging, an embedded package of most interest at the moment. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature for several years thanks to high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, and with many other developments from OSATs and an aggressive technology from TSMC (inFO). 2016 was a turning point for the Fan-Out market with Apple A1O application processor being packaged using TSMC solution. This partnership changed the game and may create a trend of acceptance of Fan-Out packages for complex applications. The market for Fan-Out packages in 2016 already reached $500M, with potential breakthrough events in store in 2017 that could make the market reach $2B in 2020. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, capable of embedding complex ICs, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC being the first example, foundries too could look at the OSATs reserved market through wafer-level packages, Samsung's reaction being interesting to follow. Each player has its own view on how to gain market share and meet the technical and financial challenges associated to Fan-Out packaging such as cost reduction, yield improvement, die shift… This work brings analysis of the strategies and offers of main players involved and describes potential success scenarios for them. It also helps to define what is Fan-Out Packaging and what are the different products and platforms, player per player, avoiding confusion already visible in the industry where many players call their solution a “Fan-Out” to benefit from the buzz created by Apple despite having significant differences from one to another (chip-first, chip-last, face-up, face-down, etc…). As package price represents the final verdict, carrier size evolution is also an important topic, both for wafers and panels, since it can help to drastically reduce the cost. This work shows that the main trend is still to keep wafer carriers but some players are already investing and developing panel-based solution and we expect volume production soon. While end-customers are pushing for a switch to panel, numerous challenges are limiting its widespread though. This work describes technical, economic and maturity challenges associated to panel manufacturing. Overall, the presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

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Fan-Out Wafer-Level-Packaging: Market and Technology Trends

International Symposium on Microelectronics ◽

10.4071/isom-2016-wa31 ◽

2016 ◽

Vol 2016 (1) ◽

pp. 000176-000179 ◽

Cited By ~ 2

Author(s):

Jérôme Azémar

Keyword(s):

Cost Reduction ◽

Flip Chip ◽

Business Models ◽

Semiconductor Industry ◽

Cost Benefit ◽

High Volume ◽

Added Value ◽

System Level ◽

Wafer Level ◽

High Expectations

Abstract The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D/3D IC solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. Embedded packages are nowadays not anymore just an interesting approach for specific applications. Benefiting from 3D TSV high cost, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players, lately most notably TSMC. In this work we will focus on one main type of embedded package of most interest at the moment: Fan-Out wafer level package. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, with many other developments from OSATs and an aggressive technology from TSMC (inFO). The market for Fan-Out packages in 2015 almost reached $500M, with potential breakthrough events in store in 2016 that could triple the 2015 market and continue further with more than 30% growth. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

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Fan-in WLP: Technology and Market Trends

International Symposium on Microelectronics ◽

10.4071/isom-2015-tp31 ◽

2015 ◽

Vol 2015 (1) ◽

pp. 000067-000072 ◽

Cited By ~ 3

Author(s):

A. Ivankovic ◽

T. Buisson ◽

S. Kumar ◽

A. Pizzagalli ◽

J. Azemar ◽

...

Keyword(s):

Flip Chip ◽

Semiconductor Industry ◽

Cost Benefit ◽

Current Status ◽

Wafer Level ◽

New Era ◽

Device Scaling ◽

Depth Analysis ◽

Application Diversification ◽

The Cost

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300mm Wafer-Level Image Sensor Packaging

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2011dpc-ta33 ◽

2011 ◽

Vol 2011 (DPC) ◽

pp. 000699-000716

Author(s):

Thorsten Matthias ◽

Bioh Kim ◽

Gerald Mittendorfer ◽

Paul Lindner ◽

Moshe Kriman ◽

...

Keyword(s):

Cost Reduction ◽

High Volume ◽

Image Sensor ◽

Consumer Electronics ◽

Glass Wafer ◽

Wafer Level ◽

Process Technology ◽

Market Growth ◽

The Cost ◽

New Applications

The image sensor market is still showing s tremendous market growth due to applications in consumer electronics, medical, automotive and communication. For a lot of new applications the image sensor packaging is in fact the enabling key technology. The introduction of wafer level packaging a couple of years ago allowed the cost reduction necessary for high volume consumer electronics. Innovative packaging concepts with TSVs and thin dies enable unmatched form factor. Currently scaling image sensor manufacturing and packaging to 300mm is the next big step forward in cost reduction. Wafer level image sensor packaging requires capping of the sensor wafer with a glass wafer. This heterogeneous integration of silicon and glass results in a variety of challenges like thermal expansion mismatch and bow and warp of the wafer stack. In this paper Tessera's OptiML Micro Via Pad technology for image sensors will be described with a special emphasis on equipment and process technology. Wafer encapsulation, via formation, electrical routing, passivation and solder bumping will be discussed.

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ANN-Based Decision Making in Station Keeping for Geotechnical Drilling Vessel

Journal of Marine Science and Engineering ◽

10.3390/jmse9060596 ◽

2021 ◽

Vol 9 (6) ◽

pp. 596

Author(s):

Murugan Ramasamy ◽

Mohammed Abdul Hannan ◽

Yaseen Adnan Ahmed ◽

Arun Kr Dev

Keyword(s):

Decision Making ◽

Water Depth ◽

Business Models ◽

Cost Benefit ◽

Cost Effective ◽

Station Keeping ◽

Operational Information ◽

Effective Option ◽

The Cost ◽

Cost Factors

Offshore vessels (OVs) often require precise station-keeping and some vessels, for example, vessels involved in geotechnical drilling, generally use Spread Mooring (SM) or Dynamic Positioning (DP) systems. Most of these vessels are equipped with both systems to cover all ranges of water depths. However, determining which system to use for a particular operational scenario depends on many factors and requires significant balancing in terms of cost-benefit. Therefore, this research aims to develop a platform that will determine the cost factors for both the SM and DP station-keeping systems. Operational information and cost data are collected for several field operations, and Artificial Neural Networks (ANN) are trained using those data samples. After that, the trained ANN is used to predict the components of cost for any given environmental situation, fieldwork duration and water depth. Later, the total cost is investigated against water depth for both DP and SM systems to determine the most cost-effective option. The results are validated using two operational scenarios for a specific geotechnical vessel. This decision-making algorithm can be further developed by adding up more operational data for various vessels and can be applied in the development of sustainable decision-making business models for OVs operators.

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Comparative economics of cashew nut kernel processing technology in Bastar region of India

Bangladesh Journal of Agricultural Research ◽

10.3329/bjar.v39i1.20166 ◽

2014 ◽

Vol 39 (1) ◽

pp. 165-172

Author(s):

Praveen Kumar Verma ◽

SK Nag ◽

SK Patil

Keyword(s):

Cost Reduction ◽

Cost Benefit ◽

Economic Viability ◽

Working Capital ◽

Cashew Nut ◽

Net Profit ◽

Cost Benefit Ratio ◽

Comparative Economics ◽

The Cost ◽

Improved Technology

The paper has studied the economic viability of improved technology (Introduced under NAIP component-3) for extraction of cashew kernel from cashew nut in Bastar region of Chhattisgarh, India. Cost concept has been used to calculate economics of cashew kernel. The technology (Boiling, steaming, cutting, drying, and peeling) has been found viable over conventional practices (Traditional manual separation by stone or hammer) on account of higher recovery of 40 percent and cost reduction by 29.71 percent. Overall net profit per unit (One unit includes one boiler, one steamer, two cutter, one dryer, six peelers and cost of land, depreciation and interest on working capital) in the case of improved technology has been estimated to be Rs 7.32 lakh. Cost of production in machine extraction practices was 202.80 Rupees per kilogram of cashew in spite of traditionally practiced 288.56 Rupees per kilogram. The cost benefit ratio was found higher in machine extraction (1.57) as compare to traditionally practiced (0.169). The mechanical decortications and separation could not only save time and money, also reduced women drudgery (due to manual breaking by stone or hammer to separate kernel). The technology has been found suitable for promotion of entrepreneurship on the processing of cashew kernel from cashew nut in the production catchments which otherwise is not properly utilized. DOI: http://dx.doi.org/10.3329/bjar.v39i1.20166 Bangladesh J. Agril. Res. 39(1): 165-172, March 2014

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Cost Comparison of Panel Level and Wafer Level Fan-out Packaging

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2380-4491-2019-dpc-presentation_ta2_001 ◽

2019 ◽

Vol 2019 (DPC) ◽

pp. 000141-000164

Author(s):

Amy Lujan

Keyword(s):

Cost Reduction ◽

Cost Comparison ◽

Cost Modeling ◽

Cost Models ◽

Wafer Level ◽

Process Flow ◽

Total Cost ◽

Large Panels ◽

The Cost ◽

The Impact

In recent years, the possibility of panels replacing wafers in some fan-out applications has been a topic of interest. Questions of cost and yield continue to arise even as the industry appears to be full steam ahead. While large panels allow for more packages to be produced at once, the cost does not scale simply based on how many more packages can be generated from a panel over a wafer. This analysis begins by breaking down the types of cost and will discuss how those types of cost are impacted (or not) by the shift from wafer to panel. Activity based cost modeling is used; this is a detailed, bottom-up approach that takes into account each type of cost for each activity in a process flow. Two complete cost models were constructed for this analysis. A variety of package sizes are analyzed, and multiple panel sizes are included as well. For each set of activities in the fan-out process flow, there is an explanation of how the process changes with the move to panel, including assumptions related to throughput, equipment price, and materials. The cost reduction that may be achieved at each package and panel size will be presented for each processing segment. The focus of this analysis is on the details of each segment of the process flow, but results for the total cost of various packages will also be presented. There is also a section of analysis related to the impact of yield on the competitiveness of panel processing.

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3D Technology Applications Market Trends & Key Challenges

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2014pdc/ta11 ◽

2014 ◽

Vol 2014 (DPC) ◽

pp. 000363-000400

Author(s):

Thibault Buisson ◽

Amandine Pizzagalli ◽

Eric Mounier ◽

Rozalia Beica

Keyword(s):

Supply Chain ◽

Business Models ◽

Semiconductor Industry ◽

High Volume ◽

Advanced Technology ◽

Passive Component ◽

Process Technology ◽

3D Integration ◽

3D Technology ◽

Major Player

Semiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging option, considered today the most advanced technology, that could enable various heterogeneous integration. Indeed such technology is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive component...) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that need to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers & 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with a multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

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Design of Power Supply Package for Electricity Sales Companies Considering User Side Energy Storage Configuration

Energies ◽

10.3390/en12173219 ◽

2019 ◽

Vol 12 (17) ◽

pp. 3219 ◽

Cited By ~ 1

Author(s):

Mu ◽

Gao ◽

Yang ◽

Liang

Keyword(s):

Energy Storage ◽

Power Supply ◽

Business Models ◽

Effective Means ◽

Cost Benefit ◽

Nsga Ii ◽

Electricity Cost ◽

Elite Strategy ◽

New Business ◽

The Cost

With the deepening of the reform of the power system, electricity sales companies are required to explore new business models and provide multi-faceted marketing programs for users. At the same time, with the reduction of energy storage (ES) costs and the gradual maturity of technology, user side ES, especially Battery ES, has become an effective means for enhancing users' power supply reliability and reducing electricity bills. Battery ES, as the standby power supply, has a vast user side application. The configuration of ES can help users to ameliorate power quality and reduce electricity cost. It is a critical strategy for electricity sales companies to improve their competitiveness as well. Firstly, this paper analyzes the user side ES and introduces the user side ES development status and relevant policies. Then, we establish an ES configuration optimization model based on the cost–benefit system. To determine the optimal ES capacity of the system’s storage capacity, non-dominated sorting genetic algorithm with elite strategy (NSGA-II) is used as the method solving model. Finally, according to the cost-effectiveness of ES and the period of a contract signed by users, a price package with ES configuration is designed for users to choose.

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ANN-Based Decision Making in Station Keeping for Geotechnical Drilling Vessel

10.20944/preprints202104.0377.v1 ◽

2021 ◽

Author(s):

Murugan Ramasamy ◽

Mohammed Abdul Hannan ◽

Yaseen Adnan Ahmed ◽

Arun Kr Dev

Keyword(s):

Decision Making ◽

Water Depth ◽

Business Models ◽

Cost Benefit ◽

Cost Effective ◽

Station Keeping ◽

Operational Information ◽

Effective Option ◽

The Cost ◽

Cost Factors

Offshore vessels (OVs) often requires precise station-keeping and some vessels, for example, vessel involves in geotechnical drilling generally use Spread Mooring (SM) or Dynamic Positioning (DP) systems. Most of these vessels are equipped with both systems to cover all ranges of water depths. However, determining which systems to use for a particular operational scenario depends on many factors and requires significant balancing in terms of cost-benefit. Therefore, this research aims to develop a platform that will determine the cost factors for both the SM and DP station keeping systems. Operational information and cost data are collected for several field operations, and Artificial Neural Networks (ANN) is trained using those data samples. After that, the trained ANN is used to predict the components of cost for any given environmental situation, fieldwork duration and water depth. Later, the total cost is investigated against water depth for both DP and SM systems to determine the most cost-effective option. The results are validated using two operational scenarios for a specific geotechnical vessel. This decision-making algorithm can be further developed by adding up more operational data for various vessels and can be applied in the development of sustainable decision-making business models for OVs operators.

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Advances in WLCSP Technologies to Enable Cost-Reduction

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2010dpc-tha32 ◽

2010 ◽

Vol 2010 (DPC) ◽

pp. 002291-002311

Author(s):

Rex Anderson ◽

R. Chilukuri ◽

B. Rogers ◽

A. Syed

Keyword(s):

Cycle Time ◽

Cost Reduction ◽

Business Models ◽

Failure Modes ◽

Time Pressure ◽

Semiconductor Industry ◽

Product Reliability ◽

Product Introduction ◽

Silicon Technology ◽

Technology Nodes

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

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