Adhesive Strength Characterization of CYTOP™: Low Temperature Wafer-Level Packaging

2006 ◽  
Author(s):  
Vikram Patil ◽  
Chad B. O'Neal
Keyword(s):  
Bond Strength ◽  
Adhesive Bonding ◽  
High Volume ◽  
Micro Electro Mechanical System ◽  
Curing Temperature ◽  
Temperature Sensitive ◽  
Glass Wafer ◽  
Mems Devices ◽  
Wafer Level ◽  
Strength Characterization

This study describes a wafer bonding technique using CYTOP™ inking method for the high volume packaging of micro-electro mechanical system (MEMS) devices. CYTOP™ is a class of perfluoro (alkenyl vinyl ether) polymer which is obtained by cyclopolymerization of perfluoro. The CYTOP™ adhesive bonding requires much lower temperature (150 to 200° C) compared to other bonding techniques such as soldering (> 250° C) or anodic (~350° C) bonding. The lower temperatures involved in the process reduce the risk of thermal damage to temperature sensitive devices during packaging. The described bonding process consists of a wet inking technique in which wet CYTOP™ ink is applied on soft cured CYTOP™ before bonding. In this study, CYTOP™ is characterized for its bonding strength and quality. The experiments are performed on silicon and glass wafer substrates. The bonded samples are pull-tested and tensile stress values are recorded at the instance of bond failure. About 90% of the samples failed at the bonding interface which indicates that the recorded stress values are the bond strength of CYTOP™. The bond strength of CYTOP™ depends upon the curing temperature and the curing time. The highest bond strength of 16. 46 MPa is recorded at 200° C and 45 min. of curing. The CYTOP™ bond strength at 200° C is comparable with bond strength of BCB at 250° C.

scholarly journals Integration Technology for Wafer-Level LiNbO3 Single-Crystal Thin Film on Silicon by Polyimide Adhesive Bonding and Chemical Mechanical Polishing

Nanomaterials ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 2554
Author(s):  
Wenping Geng ◽  
Xiangyu Yang ◽  
Gang Xue ◽  
Wenhao Xu ◽  
Kaixi Bi ◽  
...  
Keyword(s):  
Thin Film ◽  
Single Crystal ◽  
Chemical Mechanical Polishing ◽  
Adhesive Bonding ◽  
Mechanical Polishing ◽  
Bonding Interface ◽  
Infrared Analysis ◽  
Mems Devices ◽  
Wafer Level ◽  
Integration Technology

An integration technology for wafer-level LiNbO3 single-crystal thin film on Si has been achieved. The optimized spin-coating speed of PI (polyimide) adhesive is 3500 rad/min. According to Fourier infrared analysis of the chemical state of the film baked under different conditions, a high-quality PI film that can be used for wafer-level bonding is obtained. A high bonding strength of 11.38 MPa is obtained by a tensile machine. The bonding interface is uniform, completed and non-porous. After the PI adhesive bonding process, the LiNbO3 single-crystal was lapped by chemical mechanical polishing. The thickness of the 100 mm diameter LiNbO3 can be decreased from 500 to 10 μm without generating serious cracks. A defect-free and tight bonding interface was confirmed by scanning electron microscopy. X-ray diffraction results show that the prepared LiNbO3 single-crystal thin film has a highly crystalline quality. Heterogeneous integration of LiNbO3 single-crystal thin film on Si is of great significance to the fabrication of MEMS devices for in-situ measurement of space-sensing signals.

300mm Wafer-Level Image Sensor Packaging

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000699-000716
Author(s):  
Thorsten Matthias ◽  
Bioh Kim ◽  
Gerald Mittendorfer ◽  
Paul Lindner ◽  
Moshe Kriman ◽  
...  
Keyword(s):  
Cost Reduction ◽  
High Volume ◽  
Image Sensor ◽  
Consumer Electronics ◽  
Glass Wafer ◽  
Wafer Level ◽  
Process Technology ◽  
Market Growth ◽  
The Cost ◽  
New Applications

The image sensor market is still showing s tremendous market growth due to applications in consumer electronics, medical, automotive and communication. For a lot of new applications the image sensor packaging is in fact the enabling key technology. The introduction of wafer level packaging a couple of years ago allowed the cost reduction necessary for high volume consumer electronics. Innovative packaging concepts with TSVs and thin dies enable unmatched form factor. Currently scaling image sensor manufacturing and packaging to 300mm is the next big step forward in cost reduction. Wafer level image sensor packaging requires capping of the sensor wafer with a glass wafer. This heterogeneous integration of silicon and glass results in a variety of challenges like thermal expansion mismatch and bow and warp of the wafer stack. In this paper Tessera's OptiML Micro Via Pad technology for image sensors will be described with a special emphasis on equipment and process technology. Wafer encapsulation, via formation, electrical routing, passivation and solder bumping will be discussed.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

Transition From MEMS Technology to Nanofabrication

2007 ◽  
Author(s):  
T. Glinsner ◽  
P. Lindner ◽  
P. Kettner ◽  
H. Kirchberger
Keyword(s):  
Nanoimprint Lithography ◽  
Low Cost ◽  
High Volume ◽  
Laboratory Research ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Industrial Processing ◽  
The Past ◽  
Mems Technology

The successful commercialization of Micro-Electro-Mechanical Systems (MEMS) from R&D to off-the-shelf products and systems has evolved from laboratory research to reliable and low cost industrial processing methods over the past 20 years. Standardization, infrastructure, roadmaps and industrial associations have been deemed key contributors for a successful transition and adaptation of microelectronics fabrication techniques to a specific nature of manufacturing MEMS devices resulted in turn key solutions for low cost, high yield and high volume wafer level processing. The need for smaller feature sizes as well as low cost manufacturing solutions has lead to significant improvements of the classical optical lithography in the past two decades following Moore’s law. Alternative patterning techniques are under development worldwide for producing patterns in the nm-range. There are similarities between MEMS and Nanofabrication requirement that allow for transitioning standardized and reliable processing technology from wafer bonding to hot embossing and from wafer level packaging to μ-CP and UV-based Nanoimprint Lithography.

Low Cost Fabrication of Micro Glass Cavities For MEMS Wafer Level and Hermetic Packaging

2011 ◽  
Vol 483 ◽  
pp. 23-33
Author(s):  
Jin Tang Shang ◽  
Jun Wen Liu ◽  
Di Zhang ◽  
Bo Yin Chen ◽  
Chao Xu ◽  
...  
Keyword(s):  
Process Parameters ◽  
Low Cost ◽  
Leakage Rate ◽  
Glass Wafer ◽  
Mems Devices ◽  
Wafer Level ◽  
Hermetic Packaging ◽  
Moving Parts

Many MEMS devices including accelerometer and gyroscopes, having moving parts, requires hermetic and low cost packaging. In this paper we propose a low cost fabricating process to prepare micro glass cavity arrays for wafer-level and hermetic packaging of MEMS. First, the fundamental of the process was discussed. Then, the process for preparing cavity arrays in Pyrex7740 glass wafer was studied experimentally. After that, the defects of the fabrication were discussed. Results show that wafer-level packaged cavities were prepared, whose diameter was controllably between 200 microns and 2000 microns. It is also disclosed that the defects could be avoided by controlling the process parameters. Results also show that the leakage rate of the single packaged cavities is below 5Χ10-9 Pa.m/s which could meet the hermetic packaging standard.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

An all-silicon process platfom for wafer-level vacuum packaged MEMS devices

2021 ◽  
pp. 1-1
Author(s):  
Mustafa Mert Torunbalci ◽  
Hasan Dogan Gavcar ◽  
Ferhat Yesil ◽  
Said Emre Alper ◽  
Tayfun Akin
Keyword(s):  
Mems Devices ◽  
Wafer Level
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