Manufacturability trade-offs of bare-die FCBGA package using thin or core-less substrate

Author(s):  
Ankita Verma ◽  
Baqar Tabrez ◽  
Lam Duong ◽  
Martin Wuest

With the increasing demand for thinner packages and higher electrical & thermal performance requirement bare-die packaging is an inevitable trend that is growing. The assembly process for manufacturing of bare die in thin or core-less substrate FCBGA packages can be challenging especially considering the effects of substrate warpage during flip chip bonding and the excessive warpage of the flip chip package. We are evaluating the manufacturing risks during bare-die FCBGA package assembly to eliminate package warpage failures using experimental techniques and improve the functional performance of the flip chip package. Various substrate & under fill materials were tested for package warpage values for warpage-free control in the full range of temperature variation. Die designs at 28nm and 40nm process nodes are extremely complex in order to achieve the highest electrical & thermal performance requirement. Die design constraints on advanced process nodes necessitate increased thermal dissipation requirements thereby requiring investigation of thermal solutions utilizing thermal interface materials (TIM) with heat-sink. The interaction of such thermal solutions with the bare die packages is evaluated using various trial and error for material selection, experimental and simulation techniques to improve the assembly process. This study also focuses on selection of thermal interface materials [TIMs] and heat sinks which have considerable impact on die integrity during package assembly and/or during process of removal for failure analysis.

Author(s):  
Prashant Singh ◽  
Seul-Yi Lee ◽  
Roop L. Mahajan

Abstract With the increasing demand for higher performance and progressive miniaturization of electronic packages, power densities and the attendant thermal dissipation requirements are expected to escalate. One of the important strategies to ensure reliable operation at the device and die (chip) levels is the use of Thermal Interface Materials (TIMs) to reduce the thermal resistance between the chip and the heat sink. In this study, we have carried out an experimental investigation to characterize thermal conductance of TIMs composed of commercially available graphene (c-rGO), graphene nanoplatlets (GNPs) of different lateral sizes (5, 15 and 25 μm), and our in-house produced thermally reduced graphene oxide at 600°C (T-rGO-600). These additives were loaded in a silicone rubber matrix where their loading fraction was fixed at 2% by weight. Thermal conductance of the resulting TIMs was determined by measuring heat flow, in steady state, through a TIM sandwiched between two metal blocks. The thermal conductance values representing the combined resistance of the composite material and the contact resistances between the TIM and the metal blocks were measured at different heat flux levels across the TIM. The results show that the thermal conductance values were independent of the heat load across the TIM as well as the TIM temperature. Further, a detailed investigation of the surface functionality and structural properties has revealed that the in-house produced T-rGO-600 has superior thermal conductance when compared to the above-mentioned carbonaceous nanomaterials, which are considered as potential candidates for enhancing thermal performance of TIMs. The data demonstrates that this result is attributable to the formation of the surface functional groups and the associated morphological changes during the reduction of graphene oxide to the T-rGO-600. Among the different GNPs tested, the GNP-15 exhibited superior thermal performance compared to the GNP-5 and GNP-25 samples.


Author(s):  
Vadim Gektin ◽  
Sai Ankireddi ◽  
Jim Jones ◽  
Stan Pecavar ◽  
Paul Hundt

Thermal Interface Materials (TIMs) are used as thermally conducting media to carry away the heat dissipated by an energy source (e.g. active circuitry on a silicon die). Thermal properties of these interface materials, specified on vendor datasheets, are obtained under conditions that rarely, if at all, represent real life environment. As such, they do not accurately portray the material thermal performance during a field operation. Furthermore, a thermal engineer has no a priori knowledge of how large, in addition to the bulk thermal resistance, the interface contact resistances are, and, hence, how much each influences the cooling strategy. In view of these issues, there exists a need for these materials/interfaces to be characterized experimentally through a series of controlled tests before starting on a thermal design. In this study we present one such characterization for a candidate thermal interface material used in an electronic cooling application. In a controlled test environment, package junction-to-case, Rjc, resistance measurements were obtained for various bondline thicknesses (BLTs) of an interface material over a range of die sizes. These measurements were then curve-fitted to obtain numerical models for the measured thermal resistance for a given die size. Based on the BLT and the associated thermal resistance, the bulk thermal conductivity of the TIM and the interface contact resistance were determined, using the approach described in the paper. The results of this study permit sensitivity analyses of BLT and its effect on thermal performance for future applications, and provide the ability to extrapolate the results obtained for the given die size to a different die size. The suggested methodology presents a readily adaptable approach for the characterization of TIMs and interface/contact resistances in the industry.


2000 ◽  
Author(s):  
Amit Devpura ◽  
Patrick E. Phelan ◽  
Ravi S. Prasher

Abstract An important aspect in electronic packaging is the heat dissipation. Flip-chip technology is widely being used to increase the rate of heat transfer from the chip. A method to further enhance the thermal conductivity is by the use of a thermal interface material between the device and the heat sink attached to it in the flip-chip technology. Percolation theory holds a key to understanding the behavior of thermal interface materials. Percolation, used widely in electrical engineering, is a physical phenomenon in which the highly conducting particles distributed randomly in the matrix form at least one continuous chain connecting the opposite faces of the matrix. This phenomenon was simulated using the matrix method, to study the effect of different shapes and size of the filler particles. The different shapes considered were spherical, vertical or horizontal rods, and flakes in horizontal or vertical orientation. The effect of the size of these particles was also examined. The results indicate that the composites with particles having the largest side in the direction of heat flow will always have a better conductivity than the particles oriented normal to it. Also, from the results, we can choose the best filler size in the composite if we know the filler concentration we are aiming at.


2018 ◽  
Vol 2018 (1) ◽  
pp. 000613-000618
Author(s):  
Dave Saums ◽  
Tim Jensen ◽  
Carol Gowans ◽  
Seth Homer ◽  
Ron Hunadi

Abstract Semiconductor test and burn-in requirements for thermal interface materials (TIMs) are challenging, with difficult mechanical reliability requirements that are not found in other types of applications for these materials. To demonstrate the ability of certain newly-developed TIMs to not only provide suitable thermal performance for the device under test and meet these mechanical requirements, a contact cycling test has been devised in three phases for evaluating TIM mechanical performance and durability.


Author(s):  
Arun Gowda ◽  
Annita Zhong ◽  
Sandeep Tonapi ◽  
Kaustubh Nagarkar ◽  
K. Srihari

Thermal Interface Materials (TIMs) play a key role in the thermal management of microelectronics by providing a path of low thermal impedance between the heat generating devices and the heat dissipating components (heat spreader/sink). In addition, TIMs need to reliably maintain this low thermal resistance path throughout the operating life of the device. Currently, several different TIM material solutions are employed to dissipate heat away from semiconductor devices. Thermal greases, adhesives, gels, pads, and phase change materials are among these material solutions. Each material system has its own advantages and associated application space. While thermal greases offer excellent thermal performance, their uncured state makes them susceptible to pump-out and other degradation mechanisms. On the other hand, adhesives offer structural support but offer a higher heat resistance path. Gels are designed to provide a level of cross-linking to allow the thermal performance of greases and prevent premature degradation. However, the degree of crosslinking can have a significant effect of the behavior of gels. In this research, TIMs with varying cross-linking densities are studied and their thermal and mechanical properties reported. The base resin systems and fillers were maintained constant, while slight compositional alternations were made to induce different degrees of cross-linking.


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