Co-optimized Reliability and Parasitic inductance in Small Footprint Vertical Silicon Carbide MOSFET

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000087-000092
Author(s):  
M. Montazeri ◽  
S. Seal ◽  
A. Wallace ◽  
A. Mantooth ◽  
D. Huitink
Keyword(s):  
Silicon Carbide ◽  
Thermal Cycling ◽  
Power Electronics ◽  
Flip Chip ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Element Analysis ◽  
Great Opportunity ◽  
Parasitic Inductance ◽  
Fea Simulation

Abstract Increasing power density in power electronics is driving a need for improved packaging methods for co-optimized high frequency performance, thermal dissipation and reliable operation, especially at high temperatures. Silicon Carbide (SiC) devices offer great opportunity as wide bandgap semiconductor devices, which maintain stability over wide temperature ranges, especially when compared to Silicon (Si) based devices. A novel flip-chip packaging technique for SiC power devices was developed at the University of Arkansas. This new package re-orients a bare die from a lateral device to a vertical device by utilizing a copper connector that routes the drain connection to the top side of the die. This study involves an investigation of achieving a co-optimized packaging configuration for thermomechanical reliability and low parasitic inductance. By orienting this SiC switch vertically, the unique 3D drain connector dramatically reduces the ringing at aggressive switching speeds used in power electronics when compared to Commercial Off The Shelf (COTS) devices. However, the design of this drain connector holds importance for high temperature operation, interconnect reliability as well as manufacturability. Effects of the packaging design, including materials, layout and solder pitch size were investigated from a thermal cycling reliability aspect. Electrical performance, such as parasitic inductances of the device, was also investigated using Finite Element Analysis (FEA) simulation. Several drain connector architectures were evaluated for their fatigue life capability of solder interconnects under thermal cycling (according to Darveaux's model) in conjunction with the parasitic inductance using FEA simulation. Based on the simulation results, an optimized architecture was selected and fabricated for prototype demonstration, and the electrical performance under double pulse test compared with state of the art devices demonstrated improvement in switching performance by reducing overshoot of voltage across the grain-source by 36% and 77% reduction of the drain current ringing during the turn-off event while eliminating voltage overshoot during turn-on event for the testing conditions.

Experimental and Numerical Investigation of the Reliability of Double-Sided Area Array Assemblies

2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Mirror Image ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Area Array ◽  
Plastic Ball

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.

Bump Electromigration and Back End Design Rules

2007 ◽  
Author(s):  
Vishal Nagaraj ◽  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Senol Pekin
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
High Current Density ◽  
Electrical Performance ◽  
High Current ◽  
Current Crowding ◽  
Element Analysis ◽  
Chip Technology ◽  
Flip Chip Packaging ◽  
Current Densities

As there is continuous demand for miniaturization of electronic devices, flip chip technology is predominantly used for high density packaging. The technology offers several advantages like excellent electrical performance and better heat dissipation ability. Original invention of flip chip packaging utilized ceramic substrates and high lead bumps. Low cost commercialization of this packaging technology, however, required organic laminate substrates coupled with SnPb eutectic bumped interconnects on the die side. While organic laminate flip chip packaging may be a good option for many low power applications, current carrying capability of the eutectic bumped interconnect causes a catastrophic failure mechanism called electromigration. Previously, researchers have identified and addressed few issues regarding electromigration. Electomigration leads to the formation of metal voids in the conductors which eventually increases the resistance drop across the conductor causing electrical opens. Electromigration is very significant at high current densities. Temperature is the other parameter of concern for electromigration. High current density causes temperature to rise due to Joule heating, there by reducing the life of package. In order to determine the factors responsible for high current densities, we formed a full factorial design of experiments (DOE) that contained parameters such as passivation opening, UBM size, UBM thickness and trace width. Finite Element Analysis (FEA) was performed in order to study the effect of above parameters on current crowding and temperature in the bumped interconnects. Based on the results, hierarchy of the most important parameters to be considered while selecting the appropriate flip chip technology is proposed.

Thermally and Electrically Enhanced Wirebond BGA

2013 ◽  
Vol 2013 (1) ◽  
pp. 000478-000483
Author(s):  
Burton Carpenter ◽  
Boon Yew Low ◽  
Leo M. Higgins ◽  
Sriram Neelakantan ◽  
Robert Wenzel ◽  
...  
Keyword(s):  
Flip Chip ◽  
Hold Time ◽  
Thermal Interface Material ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Package Design ◽  
Die Attach ◽  
Bga Package ◽  
End Use ◽  
Set Up

Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently, devices are designed into Flip Chip (FC) packages where the previous generations were in Wire Bond (WB) because FC typically provides superior thermal dissipation and lower package electrical parasitics than WB packages. However, FC packages usually have higher costs for mid-range IO (500–800). An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (Thermally Enhanced PBGA type 2). The 500μm barrier of mold compound between the die and heatspreader in the TEPBGA-2 is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader that is adhesively bonded to the mold cap and thermally coupled to the die using a 40μm TIM (thermal interface material). Improvements to substrate design rules and the die attach process that enabled the Enhanced WB design to shorten bond wires by 40% and improved electrical performance. Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, that dissipates up to 15W in some end-use applications, approximately 2× the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement. This paper will present the package design, thermal and electrical simulation and measurement results.

An Optical Method for Measuring the Two-Dimensional Surface Curvatures of Electronic Packages During Thermal Cycling

2000 ◽  
Vol 123 (3) ◽  
pp. 196-199 ◽  
Author(s):  
Yong Du ◽  
Jie-Hua Zhao ◽  
Paul Ho
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Thermal Cycling ◽  
Optical Method ◽  
Flip Chip ◽  
Laser Beams ◽  
Electronic Packages ◽  
Two Dimensional ◽  
Element Analysis ◽  
Dimensional Surface

An optical method was developed to measure the two-dimensional (2D) surface curvatures of electronic packages by employing four laser beams. Each laser beam measures the slopes of the surface at the incident point along two perpendicular directions. By combining four pairs of slopes, the 2D surface curvatures of the package can be calculated. The surface warpage of an underfilled flip-chip package during thermal cycling was measured by this method and the result was verified by finite element analysis (FEA). Both experimental and FEA results show that the surface warpage is almost a linear function of temperature between 25°C and 150°C for the measured package.

Comparative Studies on Solder Joint Reliability of Plastic and Ceramic Ball Grid Array Packages of the Same Form Factor Under Power and Accelerated Thermal Cycling

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
S. B. Park ◽  
Rahul Joshi ◽  
Izhar Ahmed ◽  
Soonwan Chung
Keyword(s):  
Thermal Cycling ◽  
Flip Chip ◽  
Thermal Loading ◽  
Ball Grid Array ◽  
Element Analysis ◽  
Severe Condition ◽  
Experimental Stress Analysis ◽  
Computational Fluid Dynamics Analysis ◽  
Accelerated Thermal Cycling ◽  
Ball Grid Array Packages

Experimental and numerical techniques are employed to assess the thermomechanical behavior of ceramic and organic flip chip packages under power cycling (PC) and accelerated thermal cycling (ATC). In PC, nonuniform temperature distribution and different coefficients of thermal expansion of each component make the package deform differently compared to the case of ATC. Traditionally, reliability assessment is conducted by ATC because ATC is believed to have a more severe thermal loading condition compared to PC, which is similar to the actual field condition. In this work, the comparative study of PC and ATC was conducted for the reliability of board level interconnects. The comparison was made using both ceramic and organic flip chip ball grid array packages. Moiré interferometry was adopted for the experimental stress analysis. In PC simulation, computational fluid dynamics analysis and finite element analysis are performed. The assembly deformations in numerical simulation are compared with those obtained by Moiré images. It is confirmed that for a certain organic package PC can be a more severe condition that causes solder interconnects to fail earlier than in ATC while the ceramic package fails earlier in ATC always.

Development of Reliable Electronic Packaging Solutions for Spacecraft Avionics Miniaturization Using Embedded Passive Devices

2003 ◽  
Author(s):  
Don Schatzel
Keyword(s):  
Thin Film ◽  
Thermal Cycling ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Electrical Performance ◽  
Passive Devices ◽  
Die Attach ◽  
Space Environments ◽  
Viable Approach

Miniaturization of electronic packages will play a key role in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing. There are still many challenges with regard to this approach that must be overcome. In order to become a viable approach these devices need to work in conjunction with other active devices such as bumped die (flip chip) that share the same substrate area. This dictates that the embedded passive devices are resistant to the subsequent assembly processes associated with die attach (temperature, pressure). Bare die will need to be mounted directly on top of one or more layers of embedded passive devices. Currently there is not an abundant amount of information available on the reliability of these devices when subjected to the high temperatures of die attach or environmental thermal cycling for space environments. Device performance must be consistent over time and temperature with minimal parasitic loss. Pretested and assembled silicon substrates with layers of embedded capacitors made with two different dielectric materials, Ta2O5 (Tantalum Oxide) and benzocyclobutene (BCB), were subjected to the die attach process and tested for performance in an ambient environment. These assemblies were subjected to environmental thermal cycling from −55°C to 100°C. Preliminary results indicate embedded passive capacitors and resistors can fulfill the performance and reliability requirements of space flight on future missions. Testing results are encouraging for continued development of integrating embedded passive devices to replace conventional electronic packaging methods.

scholarly journals Liquid-Cooled Aluminum Silicon Carbide Heat Sinks for Reliable Power Electronics Packages

2019 ◽  
Vol 141 (4) ◽  
Author(s):  
Darshan G. Pahinkar ◽  
Lauren Boteler ◽  
Dimeji Ibitayo ◽  
Sreekant Narumanchi ◽  
Paul Paret ◽  
...  
Keyword(s):  
Heat Transfer ◽  
Silicon Carbide ◽  
Thermal Cycling ◽  
Power Electronics ◽  
Coefficient Of Thermal Expansion ◽  
Base Plate ◽  
Transfer Coefficients ◽  
Pin Fins ◽  
Aluminum Silicon Carbide ◽  
Aluminum Silicon

With recent advances in the state-of-the-art of power electronic devices, packaging has become one of the critical factors limiting the performance and durability of power electronics. To this end, this study investigates the feasibility of a novel integrated package assembly, which consists of copper circuit layer on an aluminum nitride (AlN) dielectric layer that is bonded to an aluminum silicon carbide (AlSiC) substrate. The entire assembly possesses a low coefficient of thermal expansion (CTE) mismatch which aids in the thermal cycling reliability of the structure. The new assembly can serve as a replacement for the conventionally used direct bonded copper (DBC)—Cu base plate—Al heat sink assembly. While improvements in thermal cycling stability of more than a factor of 18 has been demonstrated, the use of AlSiC can result in increased thermal resistance when compared to thick copper heat spreaders. To address this issue, we demonstrate that the integration of single-phase liquid cooling in the AlSiC layer can result in improved thermal performance, matching that of copper heat spreading layers. This is aided by the use of heat transfer enhancement features built into the AlSiC layer. It is found that, for a given pumping power and through analytical optimization of geometries, microchannels, pin fins, and jets can be designed to yield a heat transfer coefficients (HTCs) of up to 65,000 W m−2 K−1, which can result in competitive device temperatures as Cu-baseplate designs, but with added reliability.

scholarly journals Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Electron Mobility Transistors ◽  
Wire Bonding ◽  
High Electron ◽  
Parasitic Inductance ◽  
Switching Performance ◽  
Turn On ◽  
Electron Mobility Transistors ◽  
Chip Technology ◽  
Switching Characteristics

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

scholarly journals An Investigation of Silica Aerogel to Reduce Acoustic Crosstalk in CMUT Arrays

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1459
Author(s):  
Varshitha Yashvanth ◽  
Sazzadur Chowdhury
Keyword(s):  
Silica Aerogel ◽  
Ultrasonic Transducer ◽  
Fluid Interface ◽  
Fractional Bandwidth ◽  
Neighboring Element ◽  
Element Analysis ◽  
Average Improvement ◽  
Capacitive Micromachined Ultrasonic Transducer ◽  
Scholte Wave ◽  
Fea Simulation

This paper presents a novel technique to reduce acoustic crosstalk in capacitive micromachined ultrasonic transducer (CMUT) arrays. The technique involves fabricating a thin layer of diisocyanate enhanced silica aerogel on the top surface of a CMUT array. The silica aerogel layer introduces a highly nanoporous permeable layer to reduce the intensity of the Scholte wave at the CMUT-fluid interface. 3D finite element analysis (FEA) simulation in COMSOL shows that the developed technique can provide a 31.5% improvement in crosstalk reduction for the first neighboring element in a 7.5 MHz CMUT array. The average improvement of crosstalk level over the −6 dB fractional bandwidth was 22.1%, which is approximately 5 dB lower than that without an aerogel layer. The results are in excellent agreement with published experimental results to validate the efficacy of the new technique.

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