Low-temperature Cu-Cu thermocompression bonding for encapsulation of a MEMS mirror

2019 ◽  
Vol 2019 (NOR) ◽  
pp. 000012-000016
Author(s):  
Henri Ailas ◽  
Jaakko Saarilahti ◽  
Tuomas Pensala ◽  
Jyrki Kiihamäki
Keyword(s):  
Low Temperature ◽  
Bond Strength ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Ex Situ ◽  
High Yield ◽  
Maximum Temperature ◽  
Wafer Level ◽  
Cu Films ◽  
Thermocompression Bonding

Abstract In this study, a low temperature wafer-level packaging process aimed for encapsulating MEMS mirrors was developed. The glass cap wafer used in the package has an antireflective (AR) coating that limits the maximum temperature of the bonding process to 250°C. Copper thermocompression was used as copper has a high self-diffusivity and the native oxidation on copper surfaces can be completely removed with combination of ex situ acetic acid wet-etch and in situ forming gas anneal. Making it suitable for a development of a low temperature bonding process. In this work, bonding on of sputtered and electrodeposited copper films was studied on temperatures ranging from 200°C to 300°C as well as the effect of pretreatment on bond strength. The study presents a successful thermocompression bonding process for sputtered Cu films at a low temperature of 200°C with high yield of 97 % after dicing. The bond strength was recorded to be 75 MPa, well above the MIL-STD-883E standard (METHOD 2019.5) rejection limit of 6.08 MPa. The high dicing yield and bond strength suggest that the thermocompression bonding could be possible even at temperatures below 200°C. However, the minimum bonding temperature was not yet determined in this study.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Sol-Gel Coating Facilitating Si-to-Si Wafer Bonding at Low Temperature

2005 ◽  
Author(s):  
J. Wei ◽  
S. S. Deng ◽  
C. M. Tan
Keyword(s):  
Low Temperature ◽  
Bond Strength ◽  
Wafer Bonding ◽  
Intermediate Layer ◽  
Bonding Temperature ◽  
Sol Gel ◽  
Bond Quality ◽  
Bubble Generation ◽  
High Bond ◽  
High Bond Strength

Silicon-to-silicon wafer bonding by sol-gel intermediate layer has been performed using acid-catalyzed tetraethylthosilicate-ethanol-water sol solution. High bond strength near to the fracture strength of bulk silicon is obtained at low temperature, for example 100°C. However, The bond efficiency and bond strength of this intermediate layer bonding sharply decrease when the bonding temperature increases to elevated temperature, such as 300 °C. The degradation of bond quality is found to be related to the decomposition of residual organic species at elevated bonding temperature. The bubble generation and the mechanism of the high bond strength at low temperature are exploited.

Characterization of Wafer Level Metal Thermo-Compression Bonding

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002326-002360
Author(s):  
Erkan Cakmak ◽  
Bioh Kim ◽  
Viorel Dragoi
Keyword(s):  
Surface Treatment ◽  
Metal Surface ◽  
Bonding Temperature ◽  
Transient Liquid Phase ◽  
Bonding Process ◽  
Bending Test ◽  
Strength Analysis ◽  
Mems Devices ◽  
Wafer Level ◽  
Bond Quality

The process of wafer-level bonding is being successfully used to form MEMS devices. Wafer level bonding may be realized by different methods such as thermo compression, transient liquid phase, anodic, glass frit, or polymer bonding. These methods have different requirements and the choice of wafer level bonding method is defined by the application type. Metal TCB has a wide variety of applications with materials of choice including Au, Cu and Al. 3D electrical connections are created by the use of Cu-Cu TCB; while CMOS MEMS devices may be realized by Al-Al TCB. In this study the wafer level bonding process of Cu-Cu and Al-Al TCB are characterized. The effects and significance of various bonding process parameters and surface treatment methods are reported on the final bond interfaces integrity and strength. Analysis methods include SAM, SEM, AFM, and four point bending test. Al-Al TCB samples were investigated on the interfacial adhesion energy and bond quality. IAE and bond quality were found to be positively correlated with bonding temperature. A bonding temperature of 500 °C or greater is necessary to obtain bond strengths of 8–10 J/m2. A positive relation between IAE and bonding temperature was observed for Cu-Cu TCB. IAE's of greater then 10 J/m2 were obtained on bonded samples that do not show a post bond residual seam on the bonding interface. An acid based pre treatment was shown to impact the surface properties of the initial metal surface hence affecting the IAE. Post bond annealing processes showed the most significant impact on the IAE of the Cu-Cu TCB system. To obtain comparable IAE values the Al-Al TCB method requires a higher bonding temperature. However the Cu-Cu TCB is sensitive to the initial metal surface condition and requires surface treatment processes prior to bonding to obtain high quality bonding results.

Low Temperature Direct Cu-Cu Immersion Bonding for 3D Integration

2009 ◽  
Vol 1156 ◽  
Author(s):  
Rahul Agarwal ◽  
Wouter Ruythooren
Keyword(s):  
Citric Acid ◽  
Low Temperature ◽  
Bonding Temperature ◽  
Atmospheric Condition ◽  
High Strength ◽  
Bonding Process ◽  
3D Integration ◽  
Temperature And Pressure ◽  
Low Temperature Bonding

AbstractHigh yielding and high strength Cu-Cu thermo-compression bonds have been obtained at temperatures as low as 175°C. Plated Cu bumps are used for bonding, without any surface planarization step or plasma treatment, and bonding is performed at atmospheric condition. In this work the 25μm diameter bumps are used at a bump pitch of 100μm and 40μm. Low temperature bonding is achieved by using immersion bonding in citric acid. Citric acid provides in-situ cleaning of the Cu surface during the bonding process. The daisy chain electrical bonding yield ranges from 84%-100% depending on the bonding temperature and pressure.

Strong, high-yield and low-temperature thermocompression silicon wafer-level bonding with gold

2004 ◽  
Vol 14 (7) ◽  
pp. 884-890 ◽  
Author(s):  
M M V Taklo ◽  
P Storås ◽  
K Schjølberg-Henriksen ◽  
H K Hasting ◽  
H Jakobsen
Keyword(s):  
Low Temperature ◽  
Silicon Wafer ◽  
High Yield ◽  
Wafer Level

Characterization of Low Temperature, Wafer-Level Gold-Gold Thermocompression Bonds

1999 ◽  
Vol 605 ◽  
Author(s):  
Christine H. Tsau ◽  
Martin A. Schmidt ◽  
S. Mark Spearing
Keyword(s):  
Low Temperature ◽  
Strain Energy Release ◽  
Constant Load ◽  
Moderate Pressure ◽  
Cohesive Failure ◽  
Wafer Level ◽  
Simultaneous Application ◽  
Mems Packaging ◽  
Thermocompression Bonding ◽  
Die Bonding

AbstractLow temperature, wafer-level bonding offers several advantages in MEMS packaging, such as device protection during aggressive processing/handling and the possibility of vacuum sealing. Although thermocompression bonding can be achieved with a variety of metals, gold is often preferred because of its acceptance in die bonding [1] and its resistance to oxidation. This study demonstrates that the simultaneous application of moderate pressure (0.5 MPa) and temperature (300°C) produces strong wafer-level bonds. A four-point benddelamination technique was utilized to quantify bond toughness. Test specimens exhibited constant load versus displacement behavior during steady state crack propagation. Two distinct fracture modes were observed: cohesive failure within the Au and adhesive failure at the Ti-Si interface. The strain energy release rate for Au-Au fracture was found to be higher than that associated with Ti-Si fracture, consistent with the greater plastic deformation that occurs in the metal during fracture.

Commercial-off-the-Shelf (COTS) 3D Integration using Low Temperature Wafer Bonding

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000836-000858 ◽  
Author(s):  
Sang Hwui Lee ◽  
Michael Khbeis
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
High Yield ◽  
Activation Process ◽  
Wafer Level ◽  
3D Integration ◽  
Release Process ◽  
Adhesive Film ◽  
Die Set ◽  
Commercial Off The Shelf

This paper reports on a successful 3D integration (3DI) of multi-purpose signal processor (MSP) chips with memory chips using die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding technologies. 3D integration enables compact systems of commercial-off-the-shelf (COTS) parts with high functionality using a wafer-level process for better thinning process uniformity and high yield throughput. The3D system is comprised of commercial Flash memory bare die and MSP bare die. The bare die are face-down aligned to a 150mm diameter silicon handle wafer with alignment marks polished silicon surface. Unique features on the commercial die are detected and used for die registration using a flip-chip bonder with vision automation. An adhesive film between the die and silicon handle wafer are used for temporary bonding. After the die-to-wafer population and bonding, the die substrates are thinned at the wafer-level to a target of 60 microns for the memory die and 25 microns for the MSP die, respectively. The thinned memory die set is permanently transferred onto a 150mm diameter silicon carrier wafer using a low temperature silicon covalent wafer bonding. Following bonding, an adhesive film release process is used to separate the memory die set from the temporary handle wafer. The thinned MSP die on a second handle wafer are then aligned to the thinned memory die set using a wafer-to-wafer alignment tool, and bonded with thin-film polyimide in a high-yield, low temperature wafer bonding process, followed by the release process to separate the MSP die set from the handle wafer. Finally, the MSP/memory stack are electrically connected using a via-last through-silicon-via (TSV) process. One of the key considerations for COTS 3DI is to meet the back-end-of-line (BEOL) thermal budgets of 350–400 Celsius. Plasma-assisted preparation facilitates the reduction in thermal budget for silicon covalent bonding and is performed at 150 Celsius, followed by a long-term annealing process at 175 Celsius. Stacking of thinned die relies on low temperature polyimide bonding that is performed at 200 Celsius. Fluorine and oxygen based plasma surface activation process and CTE-matched polyimide bonding play a critical role in enabling the low temperature bonding for this 3D MSP/memory integration. The thinning and bonding processing details that are presented in this paper are essential for COTS 3DI but can also be applied to several low-profile multi-chip module and packaging applications.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

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