Package Reliability and Integrity Improvements for a Thermally Enhance Non-Conductive Die Attach Adhesive for ASIC Devices on Exposed Pad Packages

2019 ◽  
Vol 2019 (1) ◽  
pp. 000091-000094
Author(s):  
Alvin Denoyo ◽  
Darwin De Lazo ◽  
Ivan Costa ◽  
Allen Menor

Abstract Polymers being used in a plastic-encapsulated integrated circuit (IC) package exposed to a humid environment absorbed moisture and expand resulting to a so called delamination failure. Weak or imperfect adhesions between the interfaces of the mold compound and adhesive unto the leadframe surface are often the main sources of these failures. In response to automotive requirements and to ensure excellent package reliability and integrity, delamination in all interfaces should then be eliminated. Thus the primary objective of this work is to fulfill the no delamination criteria in all interfaces after moisture soak for an exposed pad package. To satisfy these requirements, activities includes leadframe design improvements, surface enhancement and bill-of-material changes. With the design improvements implemented, still the material compatibility plays an important role in achieving improved package reliability.

1995 ◽  
Vol 390 ◽  
Author(s):  
Steven K. Groothuis ◽  
K. Gail Heinen

ABSTRACTMaking the transition from mechanical testing of mold compounds to actual Integrated Circuit (IC) plastic package reliability requires an understanding of material behavior under the influences of moisture, temperature, and varying load conditions. This paper will focus on the role of material strengths, strain energy, and nonlinear effects in determining plastic package reliability. Examples of correlation between materials testing and reliability data will be presented.


Author(s):  
William Eslinger

Abstract This case study details a latent integrated circuit (IC) failure mechanism caused by the migration of silver (Ag) inside the encapsulated package of a CMOS (complementary metal-oxide-silicon) device. The plating of the lead frame was the source of the migrated silver, which was redeposited along the interface between the die attach epoxy and the plastic encapsulate. The resulting metallic ‘stringers’ bridged adjacent lead frame legs over distances greater than 150 μm and created relatively low-resistance paths capable of carrying 100’s of micro-amps.


Author(s):  
Thomas M. Moore

In the last decade, a variety of characterization techniques based on acoustic phenomena have come into widespread use. Characteristics of matter waves such as their ability to penetrate optically opaque solids and produce image contrast based on acoustic impedance differences have made these techniques attractive to semiconductor and integrated circuit (IC) packaging researchers.These techniques can be divided into two groups. The first group includes techniques primarily applied to IC package inspection which take advantage of the ability of ultrasound to penetrate deeply and nondestructively through optically opaque solids. C-mode Acoustic Microscopy (C-AM) is a recently developed hybrid technique which combines the narrow-band pulse-echo piezotransducers of conventional C-scan recording with the precision scanning and sophisticated signal analysis capabilities normally associated with the high frequency Scanning Acoustic Microscope (SAM). A single piezotransducer is scanned over the sample and both transmits acoustic pulses into the sample and receives acoustic echo signals from the sample.


2013 ◽  
Vol 2013 (1) ◽  
pp. 000152-000157
Author(s):  
Susie Johansson ◽  
John Dzarnoski

Miniaturization of everyday products has been driving sales for some time and continues to fuel the consumer market. Everyone expects size reduction with each new product generation [1], [2]. Almost everything has electronics inside that must get smaller. There is no market demanding smaller devices that are faster, more capable, more feature-rich than that of the hearing aid industry. While radios, Bluetooth wireless systems and other accessories are added to hearing instruments feature lists, the consumer nonetheless continues to wish for them to be even smaller. Advancements in circuit fabrication, component shrinkage and die consolidation have aided the industry in satisfying this need. However, as this demand continues and even intensifies, current surface mount device assembly materials are becoming inadequate and the limiting factor for overall circuit size reduction; specifically, the die attachment, protection and reinforcement process is limiting how small hearing aid circuits can be. For hearing aids, the addition of more features and connection to more accessories each require a number of integrated circuits and associated passives attached to a flexible circuit. These circuits are invariably bent and twisted during assembly, up to 180°, requiring the integrated circuit solder joints to be reinforced by underfilling to prevent detachment. Unfortunately, the underfilling process is time-consuming and the capillary action necessary for its success is finicky. Even more unfavorably, a designated “keep out” area for other components must surround the die to be underfilled to allow for the dispensing equipment to access the die, reducing the useable board space and limiting the overall possibility of circuit size reduction. Additionally, the underfill material must stay away from circuit board edges and areas to be bent during final assembly. In an attempt to increase useable circuit board space, decrease overall circuit board size, and reduce assembly steps, the application of two epoxy flux materials for die attach fluxing and underfilling of hearing aids was evaluated. Epoxy flux is a relatively new material, which combines the functionality of flux and underfill into a single step. Epoxy flux's application, while eliminating steps, would more significantly eliminate the necessary “keep out” areas around die and allow for more densely placed surface mount components. The epoxy flux materials were applied by both printing and dipping, and then evaluated using x-ray imaging, scanning acoustic microscope imaging, die peel testing, multiple reflow integrity testing and die shear testing.


Author(s):  
Michael D. Capili

In the Semiconductor Industry, the delamination performance of integrated circuit packaging is being aggressively improved. However, this task is complicated and difficult, as the defective failure is highly dependent on the compatibility of the material characteristics that may affect the entire Integrated Circuit package system under certain stress levels, both mechanical and thermal. This research work aims to study Die Attach process optimization in DAF adhesive for Nickel-Palladium-Gold Die Pad leadframe to achieve maximum reliability performance under IPC / JEDEC Moisture Sensitivity Level 1 (MSL1) at 260°C reflow. Strategic optimization of the Die Attach process is needed to ensure robust reliability. And one of the solutions is to apply the Scrubbing method, which is a machine feature used at a constant temperature to aid in the wetting of adhesives and the removal of voids.


Author(s):  
Frederick Ray Gomez ◽  
Rennier Rodriguez ◽  
Nerie Gomez

Die attach film (DAF) voids detection is one of the challenges during the introduction of non-conductive adhesives for integrated circuit products affecting production control robustness and detection. In this paper, a specialized tool capable to distinguish and quantify the amount of DAF voids is presented wherein the implementation of semi-auto grid lines generates more precise measurement and correct defect call-out. The tool is proposed as an alternative option for x-ray inspection that is found to be incapable in proper detection and accurate measurement of gaps and un-occupied area within the adhesive thickness that produces over estimation of production rejects.


2019 ◽  
Vol 16 (1) ◽  
pp. 13-20
Author(s):  
Ephraim Suhir ◽  
Sung Yi ◽  
Jennie S. Hwang ◽  
Reza Ghaffarian

Abstract The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of Integrated Circuit (IC) packages with conventional (small) standoff heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: attributes of the manufacturing process, solder material properties, and design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the Printed Circuit Board (PCB)-package assembly and particularly by the differences in the thermally induced curvatures of the PCB and the package. In this analysis, the stress and warpage issue is addressed using an analytical predictive stress model. The model is a modification and an extension of the model developed back in 1980s by the first author. It is assumed that it is the difference in the postfabrication deflections of the PCB-package assembly that is the root cause of the solder material failures and particularly and perhaps the HnP defects. The calculated data based on the developed stress model suggest that the replacement of the conventional ball grid array (BGA) designs with designs with elevated standoff heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design, referred to as BGA, and a design with solder joints with elevated standoff heights, referred to as column grid array (CGA), are compared. The computed data indicated that the effective stress in the solder material was relieved by about 40% and the difference between the maximum deflections of the PCB and the package was reduced by about 60%, when the BGA design was replaced by a CGA system. Although no definite proof that the use of solder joints with elevated standoff heights will lessen the package propensity to the HnP defects is provided, the authors nonetheless think that there is a reason to believe that the application of solder joints with elevated standoff heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.


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