scholarly journals Electromigration in Power Devices: A Combined Effect of Electromigration and Thermal Migration

2021 ◽  
Vol 18 (1) ◽  
pp. 1-6
Author(s):  
Hao Zhuang ◽  
Robert Bauer ◽  
Markus Dinkel
Keyword(s):  
Current Density ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Stress Test ◽  
Test System ◽  
Power Device ◽  
Current Direction ◽  
Power Devices ◽  
Thermal Migration ◽  
Maximum Current

Abstract In the power semiconductor industry, there is continuous development toward higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~9× for PQFN 5 × 6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger than a 100-μm microbump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development toward higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5 × 6 package to study the EM behavior of a power device soldered on a printed circuit board (PCB). We employed the highest current (120 A) and temperature (150°C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1,200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168°C) than the PCB board which was kept under temperature control at 150°C. This temperature difference resulted in a thermal gradient between the device and PCB, which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the metal-oxide-semiconductor field-effect transistor chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Electromigration in Power Devices

2020 ◽  
Vol 2020 (1) ◽  
pp. 000078-000084
Author(s):  
Hao Zhuang ◽  
Robert Bauer ◽  
Markus Dinkel
Keyword(s):  
Current Density ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Stress Test ◽  
Test System ◽  
Circuit Board ◽  
Power Device ◽  
Current Direction ◽  
Power Devices ◽  
Maximum Current

Abstract In the power semiconductor industry, there is continuous development towards higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~8x for QFN 5×6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger compared to a 100 μm micro-bump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development towards higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5×6 package to study the EM behavior of a power device soldered on a Printed Circuit Board (PCB). We employed the highest current (120 A) and temperature (150 °C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168 °C) than the PCB board which was kept under temperature control at 150 °C. This temperature difference resulted in a thermal gradient between the device and PCB which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the MOSFET chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Precise Chip Joint Method with Sub-micron Au Particle for High-density SiC Power Module Operating at High Temperature

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000254-000259 ◽  
Author(s):  
Fumiki Kato ◽  
Fengqun Lang ◽  
Simanjorang Rejeki ◽  
Hiroshi Nakagawa ◽  
Hiroshi Yamaguchi ◽  
...  
Keyword(s):  
Shear Strength ◽  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
High Density ◽  
Cathode Side ◽  
Module Structure ◽  
Power Devices ◽  
Power Module ◽  
Joint Method

In this work, a novel precise chip joint method using sub-micron Au particle for high-density silicon carbide (SiC) power module operating at high temperature is proposed. A module structure of SiC power devices are sandwiched between two silicon nitride-active metal brazed copper (SiN-AMC) circuit boards. To make a precise position and height control of the chip bonding, the top side (gate/source or anode pad side) of SiC power devices are flip-chip bonded to circuit electrodes using sub-micron Au particle with low temperature (250°C) and pressure-less sintering. The accuracy of the bonding position of chips was less than 10 μm and the accuracy of the height after bonding chips was less than 15 μm. Mechanical shear fatigue tests for flip-chip bonded SiC Schottky barrier diode (SBD) were carried out. As a result, initial shear strength of the joint was 36 MPa. The shear strength of 43 MPa is obtained after storage life test (500 hours at 250°C), and also 35 MPa is obtained even after thermal cycle stress test (1000 cycles between −40°C and 250°C). The flip-chip bonding of SiC-JFET is successfully realizedon the substrate without short or open failure electrically. Finally we joint the backside of the SiC-JFET (drain side) and the SiC-SBD (cathode side) to each circuit electrodes at once by means of reflow process with Au-12%Ge solder. The structured sandwich SiC power module was also successfully formed.

Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices

2016 ◽  
Vol 858 ◽  
pp. 978-981 ◽  
Author(s):  
Hossein Elahipanah ◽  
Arash Salemi ◽  
Carl Mikael Zetterling ◽  
Mikael Östling
Keyword(s):  
Electric Field ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Current Density ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Power Devices ◽  
Process Step ◽  
Single Finger ◽  
Maximum Current

High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) were fabricated and optimized in terms of the length (LJTE) and remaining dose (DJTE) of JTEs. It is found that for a given total termination length (Σ LJTEi), a decremental JTE length from the innermost edge to the outermost mesa edge of the device will result in better modification of the electric field. A breakdown voltage (BV) of 4.95 kV is measured for the modified device which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches were fabricated. The maximum current gain of 40 is achieved for a single finger device with the emitter width of 40 µm at IC = 0.25 A (JC = 310 A/cm2) which corresponds to RON = 33 mΩ.cm2. It is presented that the current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

scholarly journals Transient Current Density in a Pair of Long Parallel Conductors

2021 ◽  
Vol 11 (15) ◽  
pp. 6920
Author(s):  
Oldřich Coufal
Keyword(s):  
Steady State ◽  
Cross Section ◽  
Current Density ◽  
Circular Cross Section ◽  
Transient Current ◽  
Constant Current ◽  
Voltage Source ◽  
Sinusoidal Voltage ◽  
Steady State Current ◽  
Maximum Current

Two infinitely long parallel conductors of arbitrary cross section connected to a voltage source form a loop. If the source voltage depends on time, then due to induction there is no constant current density in the loop conductors. It is only recently that a method has been published for accurately calculating current density in a group of long parallel conductors. The method has thus far been applied to the calculation of steady-state current density in a loop connected to a sinusoidal voltage source. In the present article, the method is used for an accurate calculation of transient current using transient current density. The transient current is analysed when connecting and short-circuiting the sources of sinusoidal, constant and sawtooth voltages. For circular cross section conductors, the dependences of maximum current density, maximum current and the time of achieving steady state on the source frequency, the distance of the conductors and their resistivity when connecting the source of sinusoidal voltage are examined.

"Anaerobic threshold": problems of determination and validation

1983 ◽  
Vol 55 (4) ◽  
pp. 1178-1186 ◽  
Author(s):  
M. P. Yeh ◽  
R. M. Gardner ◽  
T. D. Adams ◽  
F. G. Yanowitz ◽  
R. O. Crapo
Keyword(s):  
Anaerobic Threshold ◽  
Stress Test ◽  
Venous Blood ◽  
Test System ◽  
Exercise Tests ◽  
Arterial Lactate ◽  
Blood Samples ◽  
Response Data ◽  
Threshold Phenomenon ◽  
Gas Response

Despite the popularity of the concept of “anaerobic threshold” (AT), the noninvasive detection criteria remain subjective, and invasive validations of AT have been based on lactate data of arterial, mixed venous, venous, and capillary blood samples without any concern for the possible lactate differences from these sources. Eight normal subjects underwent two exercise tests on a bicycle ergometer. The protocol consisted of 3 min of rest, 3 min of 0 work load, and a 20 W/min ramp (1 W/3 s) until exhaustion. Simultaneous arterial and venous blood samples were drawn during the second test. Noninvasive gas response data were measured using a computerized breath-by-breath stress test system. Threshold phenomenon of the lactate accumulation was not found. The arterial lactate levels increased continuously after the start of the exercise ramp. The rise in venous lactate lagged behind the rise of the arterial lactate by about 1.5 min, and therefore venous lactate was not considered suitable for AT detection. Four independent exercise physiologists determined AT from the gas response data. The reviewer variability (avg range 16%) of AT for a given subject was representative of AT values reported for untrained and trained individuals (40-70% maximum O2 consumption). We concluded that 1) AT is not detectable using invasive methods (arterial and venous lactates); and 2) the noninvasive gas response determination has such a large range of reviewer variability that it is unsuitable for clinical use.

scholarly journals FCCSP IMC growth under reliability stress follows automotive criteria

2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
Temperature Cycling ◽  
Content Type ◽  
Initial Stage ◽  
High Temperature Storage ◽  
Temperature Cycling Test ◽  
Temperature Storage

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

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