Bond Over Active Circuitry Design for Reliability

2011 ◽  
Vol 2011 (1) ◽  
pp. 000249-000257
Author(s):  
Stevan Hunter ◽  
Jose Martinez ◽  
Cesar Salas ◽  
Marco Salas ◽  
Jason Schofield ◽  
...  

This paper discusses layout design rules for successful Cu wire bond-over-active-circuitry (BOAC) in 0.18 micron and other IC technologies having Al metallization interconnects (two-level metal and up) in SiO2 dielectric, with W vias. The resulting bond pad structures effectively address BOAC pad reliability concerns, permitting Au or Cu wire bonding on relatively thin top metal. Cu wire bond is attractive on BOAC designs for lower cost than Au wire, while improving the thermal capability of the product. But Cu wire bond has presented even more challenges than Au wire bond due to higher stress to the pads during bonding, typically leading to increases in underlying films deformation and cracking. The new BOAC pad layout rules are based on the physical thin films principles, substantiated and refined through analysis of a large volume of experimental and product qualification data in various IC technologies. Interconnect layout beneath pads which follows the BOAC design rules creates more robust bond pad structures, preventing Al films deformation while strengthening the dielectric against cracking, and permitting free-form Si device design beneath. Substantial freedom in interconnect design is permitted in all metal layers beneath the pad, but the rules for top via and top-metal-minus-one layers are more restrictive than the rest. The BOAC design rules do not require any changes in wafer processing, they do not prevent the adding of redistribution or other layers for solder bumping or the like, but they do enable smaller die size and less expensive wire bond without jeopardizing bonding reliability.

Author(s):  
Steve K. Hsiung ◽  
Kevan V. Tan ◽  
Andrew J. Komrowski ◽  
Daniel J. D. Sullivan ◽  
Jan Gaudestad

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.


Coatings ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 190
Author(s):  
Florian Cougnon ◽  
Mathias Kersemans ◽  
Wim Van Paepegem ◽  
Diederik Depla

Due to the low heat flux towards the substrate, magnetron sputter deposition offers the possibility to deposit thin films on heat sensitive materials such as fiber-reinforced polymers, also known as composite materials. Passive thermal probe measurements during the sputter deposition of metal layers show indeed that the temperature increase remains well below 25 °C for film thicknesses up to 600 nm. The latter thickness threshold is based on the influence of embedded metal films on the adhesion of the composite plies. Films thicker than this threshold deteriorate the mechanical integrity of the composite. The introduction of the uncured composite in the vacuum chamber strongly affects the base pressure by outgassing of impurities from the composite. The impurities affect the film properties as illustrated by their impact on the Seebeck coefficient of sputter deposited thermocouples. The restrictions to embed thin films in composites, as illustrated by both the heat flux measurements, and the study on the influence of impurities, are however not insurmountable. The possibility to use embedded thin films will be briefly demonstrated in different applications such as digital volume image correlation, thermocouples, and de-icing.


Nano Research ◽  
2015 ◽  
Vol 9 (1) ◽  
pp. 158-164 ◽  
Author(s):  
Zhiling Xu ◽  
Weina Zhang ◽  
Jiena Weng ◽  
Wei Huang ◽  
Danbi Tian ◽  
...  

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
T.-H.-N. Dinh ◽  
E. Martincic ◽  
E. Dufour-Gergam ◽  
P.-Y. Joubert

This paper reports on the optimization of flexible PDMS-based normal pressure capacitive microsensors dedicated to wearable applications. The operating principle and the fabrication process of such microsensors are presented. Then, the deformations under local pressure of PDMS thin films of thicknesses ranging from 100 μm to 10 mm are studied by means of numerical simulations in order to foresee the sensitivity of the considered microsensors. The study points out that, for a given PDMS type, the sensor form ratio plays a major role in its sensitivity. Indeed, for a given PDMS film, the expected capacitance change under a 10 N load applied on a 1.7 mm radius electrode varies from a few percent to almost 40% according to the initial PDMS film thickness. These observations are validated by experimental characterizations carried out on PDMS film samples of various thicknesses (10 μm to 10 mm) and on actual microsensors. Further computations enable generalized sensor design rules to be highlighted. Considering practical limitations in the fabrication and in the implementation of the actual microsensors, design rules based on computed form ratio optimization lead to the elaboration of flexible pressure microsensors exhibiting a sensitivity which reaches up to10%/N.


1997 ◽  
Vol 476 ◽  
Author(s):  
Wei-Tsu Tseng ◽  
Li-Wen Chen ◽  
G.-C. Tu

AbstractVariations in stress and grain size of Ti- and TiN- capped Al thin films passivated by fluorinated silicon dioxide (SiOF) during repetitive thermal cycling are investigated. The amount of stress relaxation, elastic and plastic behavior of these thin film structures are compared. Ti and TiN cap layers strengthen the single Al film significantly while the presence of SiOF induces plastic deformation of metal layers. Less grain growth is associated with a dielectric passivated Al film. The penetration of fluorine into Al upon annealing can be reduced by a TiN barrier layer.


VLSI Design ◽  
2000 ◽  
Vol 10 (3) ◽  
pp. 249-263
Author(s):  
Zhen Luo ◽  
Margaret Martonosi ◽  
Pranav Ashar

Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking (DRC) were hobbled by the fact that it is often impractical to build a different rulechecking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. It can garner impressive speedups over software approaches, while retaining the flexibility needed to change the rule checker as rules or processes change.Our work proposes an edge-endpoints-based method for performing Manhattan geometry checking and a general scalable architecture for DRC. We then demonstrate our approach by applying this architecture to a set of design rules for MOSIS SCN4N_SUB process. We have implemented several design rule checks within a single Xilinx XC4013 FPGA and demonstrated overall speedups in excess of 25X over software methods. We have used a Compaq Pamette board to do the hardware prototyping and have achieved a clock rate of 33 MHz.


Sign in / Sign up

Export Citation Format

Share Document