Electroplating with Dielectric Bridges

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000590-000610
Author(s):  
Gene Stout ◽  
Doug Scott ◽  
Anthony Curtis ◽  
Guy Burgess ◽  
Theodore G. Tessier
Keyword(s):  
Seed Layer ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
High Volume ◽  
Wafer Level ◽  
Semiconductor Wafer ◽  
Front End ◽  
Dielectric Layers ◽  
Alternative Means ◽  
Assembly Operations

The electroplating of underlying metal redistribution layers, under-bump metallization (UBM) layers, WLCSP, Cu pillar and other flip chip applications is well established in the semiconductor industry. The use of semi-additive plating can sometimes be adversely affected by the absence of plating occurring in all targeted locations or with plating non-uniformity as a result of front-end fab related structural anomalies. Subsequent analysis has routinely determined that the previously deposited metal seed layer had been discontinuous due to the topography of wafer features. The most predominant types of topographical issues causing discontinuity in the seed layer are related to adverse sidewall profiles of an underlying dielectric layer or an edge of die feature. Typically die streets are kept clear of certain dielectric layers to avoid complications from saw tool wear and residual defects. As such, these particular dielectric layers are usually terminated at or near each die edge on a semiconductor wafer during processing. Introducing dielectric bridges over the dicing streets provides additional assurances an alternative means to significantly improve the ability to uniformly plate on all targeted die by creating an electrically continuous seed layer pathway while still allowing for subsequent wafer dicing with minimal blade wear, die chipping or residual dielectric issues. FCI has developed and successfully uses this patent pending method to insure the uniform electroplating of metallization layers for a wide variety of applications. This paper will highlight the advantages of this wafer level processing strategy in a high volume, high mix wafer bump fabrication facility including improvements in processing quality and consistency. The transparency on deploying this front-end process change on back-end assembly operations and device reliability will also be addressed.

Fan-Out Wafer-Level-Packaging: Market and Technology Trends

2016 ◽  
Vol 2016 (1) ◽  
pp. 000176-000179 ◽  
Author(s):  
Jérôme Azémar
Keyword(s):  
Cost Reduction ◽  
Flip Chip ◽  
Business Models ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
High Volume ◽  
Added Value ◽  
System Level ◽  
Wafer Level ◽  
High Expectations

Abstract The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D/3D IC solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. Embedded packages are nowadays not anymore just an interesting approach for specific applications. Benefiting from 3D TSV high cost, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players, lately most notably TSMC. In this work we will focus on one main type of embedded package of most interest at the moment: Fan-Out wafer level package. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, with many other developments from OSATs and an aggressive technology from TSMC (inFO). The market for Fan-Out packages in 2015 almost reached $500M, with potential breakthrough events in store in 2016 that could triple the 2015 market and continue further with more than 30% growth. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

Fan-in WLP: Technology and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000067-000072 ◽  
Author(s):  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
A. Pizzagalli ◽  
J. Azemar ◽  
...  
Keyword(s):  
Flip Chip ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
Current Status ◽  
Wafer Level ◽  
New Era ◽  
Device Scaling ◽  
Depth Analysis ◽  
Application Diversification ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

Assembly Equipment Requirements for Next Generation Advanced Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann
Keyword(s):  
Capital Investment ◽  
Flip Chip ◽  
High Volume ◽  
Electrical Performance ◽  
Wafer Level ◽  
Considerable Uncertainty ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
The Impact ◽  
3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Fan-Out Packaging: Technologies and market trends

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-35 ◽  
Author(s):  
Jerome Azemar
Keyword(s):  
Cost Reduction ◽  
Business Models ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
High Volume ◽  
Main Trend ◽  
Wafer Level ◽  
Device Scaling ◽  
Application Processor ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level solution aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. In this work we will focus on Fan-Out packaging, an embedded package of most interest at the moment. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature for several years thanks to high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, and with many other developments from OSATs and an aggressive technology from TSMC (inFO). 2016 was a turning point for the Fan-Out market with Apple A1O application processor being packaged using TSMC solution. This partnership changed the game and may create a trend of acceptance of Fan-Out packages for complex applications. The market for Fan-Out packages in 2016 already reached $500M, with potential breakthrough events in store in 2017 that could make the market reach $2B in 2020. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, capable of embedding complex ICs, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC being the first example, foundries too could look at the OSATs reserved market through wafer-level packages, Samsung's reaction being interesting to follow. Each player has its own view on how to gain market share and meet the technical and financial challenges associated to Fan-Out packaging such as cost reduction, yield improvement, die shift… This work brings analysis of the strategies and offers of main players involved and describes potential success scenarios for them. It also helps to define what is Fan-Out Packaging and what are the different products and platforms, player per player, avoiding confusion already visible in the industry where many players call their solution a “Fan-Out” to benefit from the buzz created by Apple despite having significant differences from one to another (chip-first, chip-last, face-up, face-down, etc…). As package price represents the final verdict, carrier size evolution is also an important topic, both for wafers and panels, since it can help to drastically reduce the cost. This work shows that the main trend is still to keep wafer carriers but some players are already investing and developing panel-based solution and we expect volume production soon. While end-customers are pushing for a switch to panel, numerous challenges are limiting its widespread though. This work describes technical, economic and maturity challenges associated to panel manufacturing. Overall, the presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview

2019 ◽  
Vol 3 (1) ◽  
pp. 69-83 ◽  
Author(s):  
Madhav Datta
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Void Formation ◽  
High Volume ◽  
Lead Free ◽  
Manufacturing Processes ◽  
Solder Paste ◽  
Chip Technology

Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so that the entire surface of the chip can be covered with bumps for the highest possible input/output (I/O) counts. The present article reviews the manufacturing processes for the fabrication of flip-chip bumps for chip–package interconnection. Various solder bumping technologies used in high-volume production include evaporation, solder paste screening and electroplating. Evaporation process produces highly reliable bumps, but it is extremely expensive and is limited to lead or lead-rich solders. Solder paste screening is cost-effective, but issues related to excessive void formation limits the process to low-end products. On the other hand, electrochemical fabrication of flip-chip bumps is an extremely selective and efficient process, which is extendible to finer pitch, larger wafers and a variety of solder compositions, including lead-free alloys. Electrochemically fabricated copper pillar bumps offer fine pitch capabilities with excellent electromigration performance. Due to these virtues, the copper pillar bumping technology is emerging as a lead-free bumping technology option for high-performance electronic packaging.

Current status and future prospects of panel level packaging

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000707-000750
Author(s):  
Santosh Kumar ◽  
Amandine Pizzagalli ◽  
Dave Towne ◽  
Thibault Buisson ◽  
Andrej Ivankovic ◽  
...  
Keyword(s):  
Semiconductor Industry ◽  
High Volume ◽  
Current Status ◽  
Flat Panel Display ◽  
Future Prospects ◽  
Wafer Level ◽  
Commercial Development ◽  
Economy Of Scale ◽  
Wafer Level Packaging ◽  
Advanced Packaging

Demand of lower cost with higher performances has driven the semiconductor industry to develop innovative solutions. One of the new approaches to reduce the overall cost is to switch from wafer to larger size panel format. The panel infrastructure has gained considerable interest from the semiconductor industry and is certainly a promising market due to its cost advantages and economy of scale benefits. Panel level manufacturing has the potential to leverage the knowledge and infrastructure of wafer level packaging as well as PCB / flat panel display / photovoltaic industries. We have identified six key packaging platforms which can be processed on larger surface (rectangular/square) such as FOWLP panel, organic interposer, glass panel interposer, hybrid interposer, embedded die as well as coreless substrate. Over the past years, it's become clear that some panel packages choices will be more suitable than others for successful commercial development. The equipment infrastructure within the advanced packaging supply chain today is mainly based on processing 300mm round wafers. However, to process larger surface, new equipment and optimized materials are required. The key question raised is when the panel industry will take off and how will it evolve? Are the supply chains ready to move to the panel scale manufacturing? What are the challenges / issues involved for the panel adoption to high volume manufacturing? This paper will try to answer these questions and discuss about the current status and future prospects of panel level packaging.

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

2015 ◽  
Vol 2015 (1) ◽  
pp. 000793-000798
Author(s):  
Keith Best ◽  
Roger McCleary ◽  
Richard Hollman ◽  
Phillip Holmes
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
High Performance ◽  
Flip Chip ◽  
Technology Development ◽  
Semiconductor Industry ◽  
Scale Up ◽  
Wafer Level ◽  
Integration Schemes ◽  
Advanced Packaging

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. In the early days of advanced packaging, C4 solder bumps were the alternative to wire bonding. Although lead-free solder remains one of the preferred methods for assembly, tall copper structures (copper pillars) are becoming the standard interconnect solution for many applications. A process of lithography and subsequent electroplating are the mainstream process for today's copper pillar formation on wafer level for high-end flip chip devices. The latest trends in advanced packaging require another technology development when it comes to copper pillars. Modern integration schemes such as 2.5D interposer as well as 3D stacking have pushed the limits of standard lithography and copper electroplating capabilities. Specifically, the need for fine-pitch high aspect ratio copper pillars represents a challenge. In addition, the trend towards rectangular panel-based packaging as seen with glass interposers or panel fan-out (P-FO) devices demands a challenging scale-up of lithography and electroplating equipment and processing capabilities. This work specifically focuses on the formation of high-aspect ratio copper pillars in excess of 100μm by means of stepper-based lithography followed by electroplating. A unique test vehicle has been created to evaluate the process latitude for lithography for different resist materials as well as the specific electroplating challenges associated with these tall and narrow structures. The paper investigates the influence of key parameters such as CD uniformity, pattern density variations and resist profile on the critically important pillar height uniformity across the wafer or panel. In addition, the resist profile behavior at the substrate interface is being examined as it influences undercut behavior during wet etch of the plating seed layer. A number of wet and dry-film resist materials and appropriate lithography processes (spin coat or laminate, expose, develop) followed by copper plating based on varying chemistries and process parameters are being explored. The paper also summarizes the current requirements for the above mentioned lithography and plating processes as seen in the industry today.

SiP Drivers and Challenges: Supply Chain Outlook and Requirements

2015 ◽  
Vol 2015 (S2) ◽  
pp. S1-S21
Author(s):  
Linda Bal
Keyword(s):  
Supply Chain ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Functional System ◽  
Next Generation ◽  
Wafer Level ◽  
Mechanical Parts ◽  
Close Proximity ◽  
And Performance

Cost pressures are driving the semiconductor industry to look for solutions that meet the challenge of expensive next generation silicon node fabrication. Simply integrating all functions in a single die may no longer be the most economical option. In addition, the need for close proximity of die and components has driven the development of packages that provide both the price and performance needs. System-in-Package (SiP) is gaining popularity as one of the most promising integration solutions. SiP is a functional system or subsystem assembled into a single package. It may contain two or more dissimilar die, typically combined with other components such as passives, filters, antennas, and/or mechanical parts. The components are mounted together on a substrate to create a customized, highly integrated product for a given application. SiPs may utilize a combination of wire bond, flip chip, wafer level packages, pre-packaged ICs such as CSPs, stacked packages, and/or stacked die. This presentation examines the role of system-in-package (SiP) discussing the formats most likely to emerge as volume packages and the supply chain requirements to produce these packages. The roles of OSATs and EMS companies are discussed with a discussion on the advantages and challenges of each.

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