Consumable Anode Process for SnAg Electroplating

2014 ◽  
Vol 2014 (1) ◽  
pp. 000117-000121
Author(s):  
Marvin Bernt ◽  
Adam McClure
Keyword(s):  
Inert Anode ◽  
Alloy System ◽  
Deposition Potential ◽  
Wafer Level ◽  
Plating Bath ◽  
Wafer Level Packaging ◽  
Free Solder ◽  
Semiconductor Packaging ◽  
Sn Anode ◽  
Liquid Concentrate

Near eutectic tin-silver (SnAg) is currently the alloy of choice for electroplated lead-free solder bumping and Cu pillar capping. While lead-tin (PbSn) is still used in some applications, there has been considerable momentum in moving away from the use of lead in semiconductor packaging. Both solders are normally electroplated as alloys with specific compositions to target a desired melting point. Since the deposition potentials of lead and tin are very close together, they plate with similar characteristics. This makes it possible for PbSn plating systems to use a consumable anode system where the anode composition matches the desired deposit composition. Metals are replenished into the bath in much the same ratio they are consumed. In a SnAg plating bath, the deposition potential of Ag is much more positive than Sn, so very low potential is required for Ag deposition. The plating rate of Ag is generally mass transfer limited. The plating rate of Sn is current controlled. While similar in concept to systems using consumable anodes for plating other metals, the SnAg alloy system presents some unique challenges. Because it is more noble, the Ag+ will deposit onto the Sn anode material by displacement reaction, and passivation will occur. Thus, the Sn anodes cannot come in contact with the Ag+ in the bath. Historically this problem is overcome by using an inert anode and metals replenishment by liquid concentrate. This paper outlines a method for plating SnAg using a consumable Sn anode, thereby reducing cost of ownership (CoO) and increasing bath stability compared to conventional SnAg wafer level packaging (WLP) plating.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Electrochemical Analysis of Aged Copper Plating Bath in Wafer Level Packaging (Part 1)

2017 ◽  
Vol 2017 (1) ◽  
pp. 000513-000516
Author(s):  
Michael Pavlov ◽  
Danni Lin ◽  
Eugene Shalyt
Keyword(s):  
Semiconductor Manufacturing ◽  
Electrochemical Analysis ◽  
Organic Additives ◽  
Wafer Level ◽  
Plating Bath ◽  
Wafer Level Packaging ◽  
Copper Electroplating ◽  
Electroplating Process ◽  
Stage 1 ◽  
Inorganic Components

Abstract Copper electroplating processes are widely used in semiconductor manufacturing, particularly during the packaging stage [1]. Copper deposition is used to build various structures including TSV, RDL, Pillars, and Micro and Mega Bumps. Those processes utilize plating solutions that contain inorganic components and organic additives [2]. During the electroplating process, the additives can partially transform into compounds that are so-called breakdown products. The presence of such breakdown products can interfere with the electrochemical analysis of organic additives. This article presents results of plating tests that show the influence of freshly produced breakdown products on analysis of organic additives. In addition, several options to eliminate this effect are presented.

ALX Polymer for Wafer Level Packaging: Mechanical Property Evaluation After Multiple Lead-Free Solder Reflows

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001054-001079
Author(s):  
Takeshi Eriguchi ◽  
Orson Wang ◽  
Kaori Tsuruoka ◽  
Yuichiro Ishibashi ◽  
Yong Zhang
Keyword(s):  
Mechanical Property ◽  
Dielectric Constant ◽  
Moisture Absorption ◽  
Lead Free ◽  
Low Dielectric Constant ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Low Dielectric ◽  
Wafer Level Packaging ◽  
Free Solder

For bumping and wafer level packaging (WLP) applications, BCB and polyimide are the predominant spin-on dielectric materials used for re-passivation, redistribution, interlayer dielectric, and stress buffer layers. Each of these materials has their respective strengths and weaknesses. BCB has exceptionally low shrinkage on cure and moisture absorption, low curing temperature, and a low dielectric constant, but is a mechanically brittle material which limits its application in bump-on-polymer applications. Polyimides are superior mechanically to BCB and are utilized more in bump-on-polymer structures, but suffer from much higher shrinkage on cure and moisture absorption (which can lead to blistering if not carefully processed), have higher dielectric constants, and have much higher cure temperatures. ALX spin-on polymer dielectric was developed to combine low shrinkage, low moisture absorption, low dielectric constant, and excellent mechanical and stress buffering properties with a cure temperature between 190C to 250C, depending on the application(1-3). Previous papers have reported the mechanical properties at 190C and the application of ALX in eutectic SnPb solder bump structures. The use of lead-free solder requires reflow temperatures up to 260C. Although ALX polymer is curable at less than 200C, the influence of lead-free solder reflow wasnft investigated. In this presentation we evaluate mechanical property changes of ALX Polymer films after different cure schedules and multiple reflows at lead-free solder temperatures. The impact of these parameters on WLP will be discussed.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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