scholarly journals A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop

2017 ◽  
Vol 7 (2) ◽  
pp. 1473-1477 ◽  
Author(s):  
H. E. Taheri
Keyword(s):  
Pump Current ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Reference Frequency ◽  
Monitor Unit ◽  
Loop Filter ◽  
Loop Bandwidth ◽  
Simulation Results ◽  
Adaptive Bandwidth ◽  
Low Phase Noise

A low power, low phase noise adaptive bandwidth phase locked loop is presented in this paper. The proposed structure benefits from a novel lock status monitor unit (LSMU) that determines loop operation and loop bandwidth. The loop filter resistance and charge pump current are inversely proportional and bandwidth to reference frequency is maintained fixed. This structure is simulated in 0.18 μm CMOS technology and simulation results are presented.

Adaptive Bandwidth PLL Design Based on Fuzzy Logic Control

2014 ◽  
Vol 543-547 ◽  
pp. 1393-1396 ◽  
Author(s):  
Lan Ying Zhang ◽  
Hai Yang Liu
Keyword(s):  
Fuzzy Logic ◽  
Fuzzy Logic Control ◽  
Fuzzy Logic Controller ◽  
Loop Filter ◽  
Logic Control ◽  
Loop Bandwidth ◽  
Simulation Results ◽  
Adaptive Bandwidth ◽  
Stability And Accuracy ◽  
Poor Stability

Based on fuzzy logic control adaptive bandwidth PLL design is presented for the problem of tracking poor stability and low accuracy when a certain type of radar tracking dynamic spacecraft. This method is mainly through fuzzy logic controller, adaptive level is determined by control rule of input respectively, and the outputs of rules are weighted combined to control the coefficient of loop filter, thus adjusting automatically the loop bandwidth, and enhancing the tracking stability of radar equipment and improving ranging accuracy. The simulation results show that the fuzzy logic control adaptive bandwidth PLL has higher tracking stability and accuracy.

A NOVEL METHOD FOR HIGH-PERFORMANCE PHASE-LOCKED LOOP

2004 ◽  
Vol 13 (01) ◽  
pp. 53-63 ◽  
Author(s):  
YOUNGSHIN WOO ◽  
YOUNG MIN JANG ◽  
MAN YOUNG SUNG
Keyword(s):  
Error Detection ◽  
High Performance ◽  
Supply Voltage ◽  
Dead Zone ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Loop Filter ◽  
Detection Range ◽  
Loop Bandwidth ◽  
Novel Method

In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.

scholarly journals A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 109
Author(s):  
Youming Zhang ◽  
Xusheng Tang ◽  
Zhennan Wei ◽  
Kaiye Bao ◽  
Nan Jiang
Keyword(s):  
Phase Noise ◽  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Chip Area ◽  
Loop Bandwidth ◽  
Bandwidth Control ◽  
Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

scholarly journals Non-Linear Mathematical Modelling for Phase Locked Loop

2018 ◽  
Vol 7 (4.10) ◽  
pp. 81
Author(s):  
Prithiviraj R ◽  
Selvakumar J
Keyword(s):  
High Speed ◽  
Linear Models ◽  
Low Cost ◽  
Phase Error ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Non Linear

Design of Phase Locked Loop (PLL) plays a vital role in transceiver field. Phase Locked Loop comprises of three blocks, namely Phase and frequency detector, loop filter and voltage-controlled oscillator. The greater advancements in CMOS technology such as high frequency, high speed, low noise and phase error leads to low-cost PLL This work aims to develop higher order non-linear models of general Phase Locked Loop. The condition of stability and choice of loop filter is also determined. Based on the analysis, the transfer function for PLL is determined.  

scholarly journals Semidigital PLL Design for Low-Cost Low-Power Clock Generation

2011 ◽  
Vol 2011 ◽  
pp. 1-9
Author(s):  
Ni Xu ◽  
Woogeun Rhee ◽  
Zhihua Wang
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detection ◽  
Linear Phase ◽  
Digital Converter ◽  
Clock Generation ◽  
Time To Digital Converter ◽  
Simulation Results

This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

scholarly journals A Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos Technology

2019 ◽  
Vol 8 (4) ◽  
pp. 3994-3999
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
High Speed ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Critical Parameters ◽  
Nanometer Cmos ◽  
Dc Power ◽  
Low Jitter ◽  
Low Phase Noise

For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents similar design for 7.5-GHz Phase locked loop in 180 nm CMOS technology. The measured phase noise of the proposed PLL with self aligned injection at 1 MHz offset is 121.14 dBc/Hz and rms jitter is 110 fs. The total dc power consumption is 13.99 mW. To support the claim process variation with design corner analysis using random variations are carried out.

scholarly journals An Efficient and Novel Design of Loop Filter, Charge Pump and VCO for PLL Using CMOS Technology

2018 ◽  
Vol 7 (3.1) ◽  
pp. 39
Author(s):  
N AshokKumar ◽  
A Kavitha
Keyword(s):  
Energy Charge ◽  
Charge Pump ◽  
Cmos Technology ◽  
Phase Lock Loop ◽  
Loop Filter ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Loop Bandwidth ◽  
Low Pass ◽  
Novel Design

This article presents an occasional energy charge pump, low pass filter and voltage supervised generator for little energy section loop. PLL are generally used for synchronization and regulate of grid- associated power electronic techniques. The article enfolds the whole circuit figure of circle filter, charge pump and voltage restrict oscillator through 1.8v energy stock. This kind uses 0.18um CMOS technology. In recent times, voltage restricted oscillator are employed for phase lock loop. A great viable loop-bandwidth plan method, derivative from a distinct -time PLL model, additional complements the jitter attributes of a PLL previously somewhat evolved via optimizing precisecircuit elements. The expressed system no longer simplest guesstimates the timing jitter of a PLL, but additionally attains the most reliable bandwidth reducing the at the whole PLL jitter.  

scholarly journals Design of All Digital Phase Locked Loop for Wireless Applications

2018 ◽  
Vol 7 (3.12) ◽  
pp. 836
Author(s):  
Swetha R ◽  
J Manjula ◽  
A Ruhan bevi
Keyword(s):  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Phase Detector ◽  
Ring Oscillator ◽  
Frequency Range ◽  
Loop Filter ◽  
Wireless Applications ◽  
Digital Phase ◽  
Operating Frequency Range

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW. 

scholarly journals An Efficient and Novel Design of Loop Filter, Charge Pump and VCO for PLL Using CMOS Technology

2018 ◽  
Vol 7 (2.20) ◽  
pp. 339
Author(s):  
Dr N.AshokKumar ◽  
Dr A.Kavitha
Keyword(s):  
Energy Charge ◽  
Charge Pump ◽  
Cmos Technology ◽  
Phase Lock Loop ◽  
Loop Filter ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Loop Bandwidth ◽  
Low Pass ◽  
Novel Design

This article presents an occasional energy charge pump, low pass filter and voltage supervised generator for little energy section loop. PLL are generally used for synchronization and regulate of grid- associated power electronic techniques. The article enfolds the whole circuit figure of circle filter, charge pump and voltage restrict oscillator through 1.8v energy stock. This kind uses 0.18um CMOS technology. In recent times, voltage restricted oscillator are employed for phase lock loop. A great viable loop-bandwidth plan method, derivative from a distinct -time PLL model, additional complements the jitter attributes of a PLL previously somewhat evolved via optimizing precisecircuit elements. The expressed system no longer simplest guesstimates the timing jitter of a PLL, but additionally attains the most reliable bandwidth reducing the at the whole PLL jitter.  

Research on the Third-Order Software Phase Locked Loop for Carrier Tracking

2013 ◽  
Vol 756-759 ◽  
pp. 2192-2196
Author(s):  
Lan Ying Zhang ◽  
Hai Yang Liu ◽  
Hong Yin Du
Keyword(s):  
Frequency Analysis ◽  
Mathematic Model ◽  
Phase Locked Loop ◽  
Third Order ◽  
Loop Filter ◽  
The Third ◽  
Management Efficiency ◽  
Simulation Results ◽  
Variable Data

The mathematic model of third-order software phase locked loop formed by three-parameter loop filter is analyzed and designed. Then, in order to solve the problem of redundancy frequency analysis bandwidth when carrier tracking, a variable data ratio software phase locked loop is studied. Finally, the method is simulated and analyzed. The simulation results demonstrate that the software phase locked loop with variable data ratio can effectively reduce the operation capacity and improve the management efficiency of the software phase locked loop.

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