A NOVEL METHOD FOR HIGH-PERFORMANCE PHASE-LOCKED LOOP
2004 ◽
Vol 13
(01)
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pp. 53-63
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Keyword(s):
In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.
2017 ◽
Vol 26
(11)
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pp. 1750179
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Keyword(s):
2017 ◽
Vol 7
(2)
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pp. 1473-1477
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Keyword(s):
2019 ◽
Vol 29
(08)
◽
pp. 2050130
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Keyword(s):
2016 ◽
Vol 4
(2)
◽
pp. 397
2013 ◽
Vol 22
(10)
◽
pp. 1340033
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Keyword(s):
Keyword(s):
2014 ◽
Vol 17
(1)
◽
pp. 62-70