scholarly journals A planar hybrid transceiving mixer at 76.5GHz for automotive radar applications

2003 ◽  
Vol 1 ◽  
pp. 207-210
Author(s):  
M. O. Olbrich ◽  
A. Grübl ◽  
R. H. Raßhofer ◽  
E. M. Biebl
Keyword(s):  
Flip Chip ◽  
Directional Coupler ◽  
Noise Figure ◽  
Low Cost ◽  
Schottky Diodes ◽  
Intermediate Frequency ◽  
Input Power ◽  
Automotive Radar ◽  
Chip Area ◽  
Noise Characteristics

Abstract. A growing number of applications for radar systems in automobiles demands for low-cost radar front-ends. A planar monostatic radar front-end is particularly suited for low cost applications as it uses only one antenna for transmission and reception and, thus, minimizes the needed chip area. Generally, in a standard homodyne radar a radio-frequency (RF) signal generated by an oscillator is used for both, the transmitted signal and the local oscillator (LO). Well controlled distribution of the input power between antenna and mixer is crucial. A transceiving mixer at 76.5GHz is presented, where this distribution is done by use of a rat-race coupler. In a conventional transceiver the oscillator signal is split into the transmitted and in the LO signal by a directional coupler. A second directional coupler is needed in order to merge the received and the LO signal at the mixer. In our design the purpose of splitting and merging the signals is realized with only one coupler. Elimination of the second coupler reduces losses significantly. The received signal is down-converted to the intermediate frequency (IF) by use of a balanced mixer. For small relative speed in a CW-Doppler-radar or short distance in a FMCWradar the IF is very small. Therefore 1/f noise is a significant value. In order to achieve good 1/f noise characteristics, Schottky diodes were used. The diodes were flip-chip bonded onto a microstrip circuit on a Al2O3 substrate. \\ The assembled transceiver was measured on-waver. An input power of 7 dBm was applied. The measured output power was 3 dBm and the conversion loss 9 dB. A noise figure of 15.3 dB was measured at 100 kHz.

scholarly journals Rectifiers’ Design and Optimization for a Dual-Channel RF Energy Harvester

2020 ◽  
Vol 10 (2) ◽  
pp. 11
Author(s):  
Davide Colaiuda ◽  
Iolanda Ulisse ◽  
Giuseppe Ferri
Keyword(s):  
Low Cost ◽  
Schottky Diodes ◽  
Input Power ◽  
Design And Optimization ◽  
Radio Frequency Energy ◽  
Dual Channel ◽  
A Value ◽  
Lumped Elements ◽  
Commercial Device ◽  
Load Pull

This paper presents the design and implementation of two front-ends for RF (Radio Frequency) energy harvesting, comparing them with the commercial one—P2110 by Powercast Co. (Pittsburgh, PA, USA) Both devices are implemented on a discrete element board with microstrip lines combined with lumped elements and are optimized for two different input power levels (−10 dBm and 10 dBm, respectively), at the GSM900 frequencies. The load has been fixed at 5kΩ, after a load-pull analysis on systems. The rectifiers stages implement two different Schottky diodes in two different topologies: a single diode and a 2-stage Dickson’s charge pump. The second one is compared with the P2110 by generating RF fields at 915 MHz with the Powercast Powerspot. The main aim of this work is to design simple and efficient low-cost devices, which can be used as a power supply for low-power autonomous sensors, with better performances than the current solutions of state-of-the-art equipment, providing an acceptable voltage level on the load. Measurements have been conducted for input power range −20 dBm up to 10 dBm; the best power conversion efficiency (PCE) is obtained with the second design, which reaches a value of 70% at 915 MHz. In particular, the proposed device exhibited better performance compared to the P2110 commercial device, allowing a maximum distance of operation of up to 22 meters from the dedicated RF power source, making it suitable even for IoT (Internet of Things) applications.

A design of analog VDD generator for passive UHF RFID Tag in 90 nm CMOS

2014 ◽  
Vol 7 (5) ◽  
pp. 507-513 ◽  
Author(s):  
Smail Hassouni ◽  
Hassan Qjidaa
Keyword(s):  
Radio Frequency Identification ◽  
Schottky Diodes ◽  
Input Power ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Chip Area ◽  
Rfid Tag ◽  
Passive Uhf Rfid ◽  
Low Power Dissipation ◽  
Simulation Results

This paper introduces a VDD generator for the ultrahigh frequency (UHF) passive Radio-frequency identification (RFID) tag, consisting of an RF-limiter, an NMOS rectifier, a DC-limiter, and a regulator. The proposed NMOS rectifier utilizes diode-connected native NMOS transistors with ultralow-threshold voltage instead of Schottky diodes. The theoretical equations for predicting the performance of the VDD generator are provided and verified by both simulation results in 90 nm CMOS process. The proposed VDD generator generates a 1.19-V stable output voltage with low-power dissipation and a 26.96% larger power conversion efficiency under conditions of 50 Ω antenna, 900 MHz, −23 dBm input power and 1 M DC output load. The chip area of the proposed VDD generator is only 105 × 85 μm. The simulation results indicated that the presented novel VDD generator is capable to provide efficient, stable, and input-independent power supply for Passive UHF RFID tag

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Investigation of Low-Frequency Noise Characteristics in Gated Schottky Diodes

2021 ◽  
Vol 42 (3) ◽  
pp. 442-445
Author(s):  
Dongseok Kwon ◽  
Wonjun Shin ◽  
Jong-Ho Bae ◽  
Suhwan Lim ◽  
Byung-Gook Park ◽  
...  
Keyword(s):  
Schottky Diodes ◽  
Low Frequency ◽  
Frequency Noise ◽  
Low Frequency Noise ◽  
Noise Characteristics

scholarly journals 60–700 K CTAT and PTAT Temperature Sensors with 4H-SiC Schottky Diodes

Sensors ◽  
2021 ◽  
Vol 21 (3) ◽  
pp. 942
Author(s):  
Razvan Pascu ◽  
Gheorghe Pristavu ◽  
Gheorghe Brezeanu ◽  
Florin Draghici ◽  
Philippe Godignon ◽  
...  
Keyword(s):  
Low Cost ◽  
Schottky Diodes ◽  
Schottky Contact ◽  
High Sensitivity ◽  
Xrd Analysis ◽  
Absolute Temperature ◽  
Lower Sensitivity ◽  
Readout Circuit ◽  
Sensing Element ◽  
High Performing

A SiC Schottky dual-diode temperature-sensing element, suitable for both complementary variation of VF with absolute temperature (CTAT) and differential proportional to absolute temperature (PTAT) sensors, is demonstrated over 60–700 K, currently the widest range reported. The structure’s layout places the two identical diodes in close, symmetrical proximity. A stable and high-barrier Schottky contact based on Ni, annealed at 750 °C, is used. XRD analysis evinced the even distribution of Ni2Si over the entire Schottky contact area. Forward measurements in the 60–700 K range indicate nearly identical characteristics for the dual-diodes, with only minor inhomogeneity. Our parallel diode (p-diode) model is used to parameterize experimental curves and evaluate sensing performances over this far-reaching domain. High sensitivity, upwards of 2.32 mV/K, is obtained, with satisfactory linearity (R2 reaching 99.80%) for the CTAT sensor, even down to 60 K. The PTAT differential version boasts increased linearity, up to 99.95%. The lower sensitivity is, in this case, compensated by using a high-performing, low-cost readout circuit, leading to a peak 14.91 mV/K, without influencing linearity.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

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