Thermal Budget for Fabricating A Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide

1995 ◽  
Author(s):  
Kunihiro Suzuki ◽  
Akira Satoh ◽  
Takayuki Aoyama ◽  
Itaru Namura ◽  
Fumihiko Inoue ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Thermal Budget ◽  
Dual Gate ◽  
Submicron Cmos

Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 1496-1502 ◽  
Author(s):  
Kunihiro Suzuki ◽  
Akira Satoh ◽  
Takayuki Aoyama ◽  
Itaru Namura ◽  
Fumihiko Inoue ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Thermal Budget ◽  
Dual Gate ◽  
Submicron Cmos

Deep Submicron CMOS Technology Using Top-Edge Round STI and Dual Gate Oxide for Low Power 256 M-Bit Mobile DRAM

2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 1892-1896 ◽  
Author(s):  
Chihoon Lee ◽  
Donggun Park ◽  
Namhyuk Jo ◽  
Chanseong Hwang ◽  
Hyeong Joon Kim ◽  
...  
Keyword(s):  
Low Power ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Dual Gate ◽  
Submicron Cmos

He plus remote plasma nitridation of ultra-thin gate oxide for deep submicron CMOS technology applications

2001 ◽  
Vol 37 (12) ◽  
pp. 788 ◽  
Author(s):  
Shyh-Fann Ting ◽  
Yean-Kuen Fang ◽  
Chien-Hao Chen ◽  
Chih-Wei Yang ◽  
Mo-Chiun Yu ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Remote Plasma ◽  
Plasma Nitridation ◽  
Technology Applications ◽  
Submicron Cmos ◽  
Thin Gate Oxide

Effect of the pre-gate oxide cleaning temperature on the reliability of GOI and devices performances in deep submicron CMOS technology

2008 ◽  
Vol 48 (11-12) ◽  
pp. 1786-1790 ◽  
Author(s):  
Y.T. Chiang ◽  
Y.K. Fang ◽  
Y.J. Huang ◽  
T.H. Chou ◽  
S.Y. Yeh ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Submicron Cmos

Effect of N+ Ion Implantation and Gox Process on in and B Channel Profile

2000 ◽  
Vol 610 ◽  
Author(s):  
G. Curello ◽  
R. Rengarajan ◽  
J. Faul ◽  
H. Wurzer ◽  
J. Amon ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Short Channel ◽  
Gate Oxide Thickness ◽  
Process Effects ◽  
Dual Gate ◽  
N Dose ◽  
The Impact

AbstractIn this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.

Ultrathin gate oxide grown on nitrogen-implanted silicon for deep submicron CMOS transistors

2001 ◽  
Vol 48 (10) ◽  
pp. 2310-2316 ◽  
Author(s):  
In-Ho Nam ◽  
Jae Sung Sim ◽  
Sung In Hong ◽  
Byung-Gook Park ◽  
Jong Duk Lee ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Cmos Transistors ◽  
Submicron Cmos

Novel Nitrogen Profile Control Technology in Ultra Thin Gate Oxide for Deep Submicron CMOS

2000 ◽  
Author(s):  
T. Ogura ◽  
H. Kotaki ◽  
S. Kakimoto ◽  
S. Zaima ◽  
Y. Yasuda
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Control Technology ◽  
Profile Control ◽  
Submicron Cmos ◽  
Thin Gate Oxide
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