Analysis of Subthreshold Swing of Junctionless Cylindrical Surrounding Gate MOSFET Using Stacked High-k Gate Oxide

2022 ◽  
Author(s):  
Hak Kee Jung
Keyword(s):  
Gate Oxide ◽  
Subthreshold Swing ◽  
High K ◽  
Surrounding Gate

scholarly journals Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

2021 ◽  
Vol 11 (1) ◽  
pp. 240
Author(s):  
Hakkee Jung
Keyword(s):  
Dielectric Constant ◽  
Oxide Film ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Asymmetric Structure ◽  
Double Gate ◽  
High K

In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

scholarly journals HfO2/TiO2/HfO2 tri-layer high-K gate oxide based MoS2 negative capacitance FET with steep subthreshold swing

AIP Advances ◽  
2020 ◽  
Vol 10 (3) ◽  
pp. 035202 ◽  
Author(s):  
Md. Sherajul Islam ◽  
Shahrukh Sadman ◽  
A. S. M. Jannatul Islam ◽  
Jeongwon Park
Keyword(s):  
Gate Oxide ◽  
Subthreshold Swing ◽  
Negative Capacitance ◽  
High K

scholarly journals Performance Assessment of Dual Material Stack Gate Oxide TFET using Dielectric Pocket

2021 ◽  
Author(s):  
Dharmender Kumar ◽  
Kaushal Nigam
Keyword(s):  
Computer Aided Design ◽  
Gate Dielectric ◽  
Gate Oxide ◽  
Subthreshold Swing ◽  
Power Switching ◽  
High K ◽  
Work Functions ◽  
High K Dielectric ◽  
The Impact ◽  
Dual Material

Abstract This paper investigates the impact of lowK and high-K dielectric pockets on DC characteristics, analog/RF, and linearity performance of dual material stack gate oxide-tunnel field-effect transistor (DMSGODP-TFET). For this, a stack gate oxide with workfunction is considered to enhance the ON-state current (ION ), lower ambipolar current (Iamb) and lower the subthreshold swing. For this case, the gate electrode is tri-segmented, named as tunnel gate (M1), control gate (M2) and auxiliary gate (M3) with different gate lengths (L1, L2, L3) and work functions (φ1, φ2, φ3), respectively. To maintain dual-work functionality, the possible combinations of these work functions are considered. Technology computer-aided design (TCAD) simulations are performed and noted that the workfunction combination (φ1 = φ3 < φ2) outperforms as compared to other combinations. Where φ1 on the source side is used to enhance the ION , while φ3 (equal to φ1) is used on the drain side to minimize the Iamb. To further enhance the device performance, a high-K dielectric pocket is considered at the drain junction to suppress the Iamb whereas, a low-K dielectric pocket is employed at the source junction to enhance the ION . Moreover, length of gate segments, dielectric pocket height, and thickness are optimized to achieve a better switching ratio, subthreshold swing (SS) and reduce the Iamb which helps in the gain of device and design of analog/RF circuits. The proposed device as compared to dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO2 gate oxide shows improvement in ION /IOF F (∼ 4.23 times), 84 % increase in transconductance (gm), 136 % increase in cut-off frequency (fT ), 126 % increase in gain bandwidth product (GBP), point subthreshold swing (15.8 mV/decade) and other significant improvements in linearity figure of merits (FOMs) making the proposed device useful for low power switching, analog/RF and linearity applications.

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

Atomic Layer Deposition of Zirconium-Based High-k Metal Gate Oxide: Effect of Si Containing Zr Precursor

2015 ◽  
Vol 15 (1) ◽  
pp. 382-385
Author(s):  
Jun Hee Cho ◽  
Sang-Ick Lee ◽  
Jong Hyun Kim ◽  
Sang Jun Yim ◽  
Hyung Soo Shin ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Gate Oxide ◽  
Metal Gate ◽  
Layer Deposition ◽  
High K

High-k gate oxide for silicon heterostructure MOSFET devices

2006 ◽  
Vol 17 (9) ◽  
pp. 689-710 ◽  
Author(s):  
S. K. Ray ◽  
R. Mahapatra ◽  
S. Maikap
Keyword(s):  
Gate Oxide ◽  
High K

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

2021 ◽  
Author(s):  
SHIKHA U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Negative Capacitance ◽  
Double Gate ◽  
High K ◽  
Gate Control ◽  
Effect Transistor ◽  
Dimensional Simulation ◽  
The Impact ◽  
Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

ION/IOFF Improvement for No Junction Surrounding Gate TFET with different high-k values

2021 ◽  
Author(s):  
P. Vimala ◽  
Manjunath Bassapuri ◽  
Harshavardhan C R ◽  
Krishna Maheshwari ◽  
Harshith P ◽  
...  
Keyword(s):  
High K ◽  
Surrounding Gate
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