Design of a 9-bit column-parallel ADC in the MAPS for real-time beam monitoring

2022 ◽  
Vol 17 (01) ◽  
pp. C01021
Author(s):  
B. Cao ◽  
Y. Wang ◽  
Y. Wen ◽  
Y. Tian ◽  
J. Liao ◽  
...  
Keyword(s):  
Small Area ◽  
Cmos Process ◽  
Effective Number ◽  
Signal To Noise ◽  
Fully Differential ◽  
Differential Nonlinearity ◽  
Active Pixel ◽  
Measurement Results ◽  
Integral Nonlinearity ◽  
Beam Monitoring

Abstract This paper describes a 2 Msps 9-bit column-parallel ADC for monolithic active pixel sensor. It is designed in fully differential cyclic architecture and takes eight clock cycles to perform a 9-bit conversion. This ADC is fabricated in a 130 nm CMOS process. Each ADC covers a small area of 100 µm × 300 µm and consumes ∼5 mW. The measurement results show that this ADC has a signal-to-noise and distortion ratio (SNDR) of 46.8 dB. The DNL (Differential Nonlinearity) and (Integral Nonlinearity) INL are 0.168 LSB and 0.112 LSB, respectively. The effective number of bits (ENOB) is 7.48 bits.

A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques

2018 ◽  
Vol 27 (07) ◽  
pp. 1850111 ◽  
Author(s):  
J. J. Ocampo-Hidalgo ◽  
J. Alducín-Castillo ◽  
I. Vázquez-Álvarez ◽  
L. N. Oliva-Moreno ◽  
J. E. Molinar-Solís
Keyword(s):  
High Resistance ◽  
Small Area ◽  
Low Voltage ◽  
Cmos Technology ◽  
Floating Gate ◽  
Process Models ◽  
Cmos Process ◽  
Gain Bandwidth ◽  
Measurement Results ◽  
Improved Performance

A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5[Formula: see text][Formula: see text]m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5[Formula: see text][Formula: see text]m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10[Formula: see text]MHz and power consumption of 120[Formula: see text][Formula: see text]W with a 1.5[Formula: see text]V single supply.

scholarly journals A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC using Simultaneous Capacitor and Op-amp Sharing Technique

2021 ◽  
Author(s):  
Shylu Sam ◽  
D. Jackuline Moni ◽  
P.Sam Paul ◽  
D. Nirmal
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Effective Number ◽  
Op Amp ◽  
Integral Nonlinearity ◽  
Silicon Based ◽  
Variable G

Abstract This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp−p,diff input signal while consuming only 7.3mW power from 1.8V supply.

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast
Keyword(s):  
High Performance ◽  
Settling Time ◽  
Cmos Process ◽  
Output Stage ◽  
Common Mode ◽  
Class Ab ◽  
Fully Differential ◽  
Op Amp ◽  
Transconductance Amplifier ◽  
Adaptive Biasing

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

DAC Testing Using Impulse Signals

2012 ◽  
Vol 19 (1) ◽  
pp. 105-114 ◽  
Author(s):  
Josef Vedral ◽  
Pavel Fexa
Keyword(s):  
Frequency Domain ◽  
Sine Wave ◽  
Testing Time ◽  
Dynamic Parameters ◽  
Effective Number ◽  
Signal To Noise ◽  
Crest Factor ◽  
Multiple Tests ◽  
Digital To Analog Converters ◽  
Band Signal

DAC Testing Using Impulse SignalsThe Multi-Tone (MT) signal with uniform amplitudes can be used for DAC testing. This paper shows an easier way to generate a MT signal using several impulse signals. The article also analyzes qualities of methods for testing the dynamic parameters of Digital to Analog Converters using an impulse signal. The MT, Damped Sine Wave (DSW) and Sinx/x (SINC) signals will be used as the source for these tests. The Effective Number of Bits (ENOB) and Signal to noise and distortion (SINAD) are evaluated in the frequency domain and they are modified using theCrest Factor(CF) correction and compared with the standard results of the Sine Wave FFT test. The first advantage of the test using an impulse signal is that you need fewer input parameters to create the band signal for testing the DAC. The second one is to reduce the testing time using a band signal in comparison with multiple tests using a single sine wave.

A Low Complexity Digital Foreground Calibration Technique for CMOS Pipelined ADCs

2019 ◽  
Vol 28 (03) ◽  
pp. 1950045
Author(s):  
Maliang Liu ◽  
Sirui Zhang ◽  
Hu Jin ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Low Complexity ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Calibration Technique ◽  
Pipelined Adcs ◽  
Integral Nonlinearity ◽  
Linear And Nonlinear ◽  
Pipeline Adcs ◽  
Foreground Calibration

A low complexity all-digital foreground calibration technique to correct linear and nonlinear errors is proposed for pipeline ADCs in this paper. This method based on the integral nonlinearity (INL) piecewise least-squares fitting improves the linearity and obtains better SNR and SFDR performance. Two switches are added to the pre-stage reference ladder to achieve an accurate measurement of the INL and DNL of the backend ADC, which reduces the calibration complexity and improves the linearity effectively. The method was applied to a 125[Formula: see text]MS/s 14-bit pipeline ADC fabricated in a 0.18[Formula: see text][Formula: see text]m CMOS process. The raw DNL and INL were 1[Formula: see text]LSB and 8[Formula: see text]LSB, respectively, without calibration, but with calibration, they were respectively improved to 0.25[Formula: see text]LSB and 2[Formula: see text]LSB. The ADC achieved an SNR of 64.5[Formula: see text]dB, an SFDR of 73.8[Formula: see text]dB and a THD of 72.7[Formula: see text]dB with a 10[Formula: see text]MHz input signal without calibration, but after calibration these figures were improved to 72.6[Formula: see text]dB, 87.5[Formula: see text]dB and 86.6[Formula: see text]dB, respectively. Its application can also be extended to SAR ADC architecture, etc.

scholarly journals Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

2018 ◽  
Vol 9 (1) ◽  
pp. 20 ◽  
Author(s):  
Yuan-Ho Chen
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Delay Lines ◽  
Differential Nonlinearity ◽  
Time Calibration ◽  
Integral Nonlinearity ◽  
Resolution Improvement ◽  
Field Programmable ◽  
Gate Array ◽  
Set Up

This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A LOW-POWER 12-BIT 250 KS/S CYCLIC ADC FOR LONG LINE ARRAY INFRARED SENSORS READOUT CIRCUIT

2011 ◽  
Vol 20 (01) ◽  
pp. 57-70 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
PENG LI ◽  
JUNWEI JIANG ◽  
ZHISHENG ZHANG
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Readout Circuit ◽  
Clock Frequency ◽  
Infrared Sensors ◽  
Differential Nonlinearity ◽  
Line Array ◽  
Long Line ◽  
Correction Technique ◽  
Cyclic Adc

A 12-bit cyclic analog to digital converter (ADC) used in long line array infrared sensors readout circuit is presented. The architecture of a low-power amplifier shared with two groups of switched capacitors is used to reduce power consumption. By adding cross-connected switches, the amplifier's offset is effectively canceled out. The improved redundant signed digit (RSD) correction technique is employed to compensate for the error resulting from the comparator's offset in sub-ADC, and the correction technique can tolerate high level of switched capacitor mismatch error, as well. The converter manufactured with Chartered 0.35 μm CMOS process exhibits 0.92 LSB maximum differential nonlinearity (DNL) and 1.5 LSB maximum integral nonlinearity (INL). The ADC has a 69.3 dB signal to noise and distortion ratio (SNDR) at 250 kS/s sample rate and 3 MHz clock frequency. It dissipates 0.8 mW with 3.3 V supply and occupies 0.22 × 0.9 mm2.

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