OFET-Based Memory Devices Operating via Optically and Electrically Modulated Charge Separation between the Semiconductor and 1,2-bis(Hetaryl)ethene Dielectric Layers

Interest in precipitation processes in silicon appears to be centered on transition metals (for intrinsic and extrinsic gettering), and oxygen and carbon in thermally aged materials, and on oxygen, carbon, and nitrogen in ion implanted materials to form buried dielectric layers. A steadily increasing number of applications of microanalysis to these problems are appearing. but still far less than the number of imaging/diffraction investigations. Microanalysis applications appear to be paced by instrumentation development. The precipitation reaction products are small and the presence of carbon is often an important consideration. Small high current probes are important and cryogenic specimen holders are required for consistent suppression of contamination buildup on specimen areas of interest. Focussed probes useful for microanalysis should be in the range of 0.1 to 1nA, and estimates of spatial resolution to be expected for thin foil specimens can be made from the curves shown in Fig. 1.

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The effect of an aluminum heat-sink layer on the laser-induced amorphization of SiOx/TeGeSn/SiOx phase-change recording films

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100154846 ◽

1989 ◽

Vol 47 ◽

pp. 574-575

Author(s):

Matthew R. Libera ◽

Martin Chen

Keyword(s):

Thin Film ◽

Phase Change ◽

Heat Sink ◽

Multilayer Film ◽

Glassy Phase ◽

Film Structure ◽

Glass Forming ◽

Active Storage ◽

Dielectric Layers ◽

Amorphous States

Phase-change erasable optical storage is based on the ability to switch a micron-sized region of a thin film between the crystalline and amorphous states using a diffraction-limited laser as a heat source. A bit of information can be represented as an amorphous spot on a crystalline background, and the two states can be optically identified by their different reflectivities. In a typical multilayer thin-film structure the active (storage) layer is sandwiched between one or more dielectric layers. The dielectric layers provide physical containment and act as a heat sink. A viable phase-change medium must be able to quench to the glassy phase after melting, and this requires proper tailoring of the thermal properties of the multilayer film. The present research studies one particular multilayer structure and shows the effect of an additional aluminum layer on the glass-forming ability.

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Epitaxial ferroelectric thin films

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100170591 ◽

1994 ◽

Vol 52 ◽

pp. 572-573

Author(s):

S. G. Ghonge ◽

E. Goo ◽

R. Ramesh ◽

R. Haakenaasen ◽

D. K. Fork

Keyword(s):

Single Crystal ◽

Work Function ◽

Nonvolatile Memory ◽

Ferroelectric Properties ◽

Electrical Contact ◽

Memory Devices ◽

Ferroelectric Films ◽

Si Substrates ◽

Electro Optic ◽

Wide Range

Microstructure of epitaxial ferroelectric/conductive oxide heterostructures on LaAIO3(LAO) and Si substrates have been studied by conventional and high resolution transmission electron microscopy. The epitaxial films have a wide range of potential applications in areas such as non-volatile memory devices, electro-optic devices and pyroelectric detectors. For applications such as electro-optic devices the films must be single crystal and for applications such as nonvolatile memory devices and pyroelectric devices single crystal films will enhance the performance of the devices. The ferroelectric films studied are Pb(Zr0.2Ti0.8)O3(PLZT), PbTiO3(PT), BiTiO3(BT) and Pb0.9La0.1(Zr0.2Ti0.8)0.975O3(PLZT).Electrical contact to ferroelectric films is commonly made with metals such as Pt. Metals generally have a large difference in work function compared to the work function of the ferroelectric oxides. This results in a Schottky barrier at the interface and the interfacial space charge is believed to responsible for domain pinning and degradation in the ferroelectric properties resulting in phenomenon such as fatigue.

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Physical stage of photosynthesis charge separation

Uspekhi Fizicheskih Nauk ◽

10.3367/ufnr.2016.02.037701 ◽

2016 ◽

Vol 186 (6) ◽

pp. 597-625 ◽

Cited By ~ 1

Author(s):

Andrei G. Yakovlev ◽

Vladimir A. Shuvalov

Keyword(s):

Charge Separation

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Adaptive Interference Mitigation for Multilevel Flash Memory Devices

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e94.a.2453 ◽

2011 ◽

Vol E94-A (11) ◽

pp. 2453-2457

Author(s):

Myeongwoon JEON ◽

Kyungchul KIM ◽

Sungkyu CHUNG ◽

Seungjae CHUNG ◽

Beomju SHIN ◽

...

Keyword(s):

Flash Memory ◽

Interference Mitigation ◽

Memory Devices

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Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices

ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2017p0574 ◽

2017 ◽

Author(s):

D. Zudhistira ◽

V. Viswanathan ◽

V. Narang ◽

J.M. Chin ◽

S. Sharang ◽

...

Keyword(s):

Failure Analysis ◽

Dielectric Films ◽

Planar Surface ◽

Chemical Methods ◽

Root Cause ◽

Essential Step ◽

Dielectric Layers ◽

Wet Chemical ◽

20 Nm ◽

Low K

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

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In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0081 ◽

2000 ◽

Author(s):

Julie Segal ◽

Arman Sagatelian ◽

Bob Hodgkins ◽

Tom Ho ◽

Ben Chu ◽

...

Keyword(s):

Failure Analysis ◽

Integrated Circuit ◽

Failure Mechanisms ◽

Memory Devices ◽

Line Defect ◽

Yield Improvement ◽

Electrical Test ◽

Large Numbers ◽

Improvement Process ◽

Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

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High-Throughput, Site-Specific Sample Prep of Ultra-Thin TEM Lamella for Process Metrology and Failure Analysis

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0391 ◽

2012 ◽

Author(s):

Roger Alvis ◽

Jeff Blackwood ◽

Sang-Hoon Lee ◽

Matthew Bray

Keyword(s):

Sample Preparation ◽

Failure Analysis ◽

Process Monitoring ◽

High Throughput ◽

Focused Ion Beam ◽

Ion Beam ◽

Memory Devices ◽

Site Specific ◽

Critical Dimensions ◽

Tem Lamella

Abstract Semiconductor devices with critical dimensions less than 20nm are now being manufactured in volume. A challenge facing the failure analysis and process-monitoring community is two-fold. The first challenge of TEM sample prep of such small devices is that the basic need to end-point on a feature-of-interest pushes the imaging limit of the instrument being used to prepare the lamella. The second challenge posed by advanced devices is to prepare an artifact-free lamella from non-planar devices such as finFETs as well as from structures incorporating ‘non-traditional’ materials. These challenges are presently overcome in many advanced logic and memory devices in the focused ion beam-based TEM sample preparation processes by inverting the specimen prior to thinning to electron transparency. This paper reports a highthroughput method for the routine preparation of artifact-free TEM lamella of 20nm thickness, or less.

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