Power IC Package Design and Analysis

2011 ◽  
pp. 57-88
Author(s):  
Yong Liu
Keyword(s):  
Power Ic ◽  
2019 ◽  
Vol 2019 (1) ◽  
pp. 000284-000288
Author(s):  
Bill Acito ◽  

Abstract Just as we transitioned from simplistic lead frames to large ball grid arrays decades ago, we find ourselves again at another inflection point in design. Originally a derivative of PCB design, IC package design finds itself straddling both PCB-style design and traditional IC design. Dimensions have shrunk to place IC package design squarely in the same design dimensions as integrated circuits. Likewise, with Moore's law rapidly losing steam to support SoC's as a system integration vehicle, advanced package technologies have been asked to fill the system enablement gap. We now see advanced packaging technologies with silicon content as the system enabler in 2.5D, 3D and fanout wafer-level packaging. Because of the silicon and small geometries, IC design flows and signoff mechanisms are being used to design the next-generation of packaged systems. Package design now finds itself in the forefront of system-level design enablement. Where once system aggregation was done in a SoC at the silicon level, packaging is being used to build a system from technology-optimized die from each functional area (memory, processing, and interfaces). Silicon is no longer just a substrate material for IC manufacturing but a “package” substrate and functional integration vehicle. As such, package design teams find themselves adding IC-based design flows and methodologies. Package designers must look to the IC tools for routing, DRC, and signoff capabilities. Designers are looking for next-generation EDA tools to support these new integration and design challenges, including LVS-like validation checks and IC-based design rules. Rather than transitioning the design team from traditional packaging tools to IC tools entirely, we propose that users can leverage complete design flows that merge the best-in-class capabilities from each of their respective design domains. Is this regard, the best-in-class capabilities can remain in their respective domains, and a design flow can be created that relies on tight integration between both domains. These flows can also leverage a single point of entry for design capture and system level management. Flows based on the system management tool and the appropriate features in each of the domains can be created that enable and optimize complex designs that meet physical, signal integrity, cost and performance requirements. We will describe how capabilities can be leveraged from both domains in a tightly coupled flow, overseen by a design system-management tool, to address the challenges of advanced-technology and silicon-based system.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000554-000569
Author(s):  
William Acito ◽  
Harry McCaleb

As package design complexity increases, and design cycle times are increasingly subject to aggressively truncated timelines, the need to achieve efficient one-pass physical routing of complex, I/O dense, IC packages becomes critical. Critical high-speed interfaces such as DDR2, DDR3, PCI Express, and HDMI now constitute a high percentage of signals in an electronic package. This presentation will focus on utilizing an integrated route-planning tool to quickly and effectively plan the physical layout of package design interfaces, without the expenditure of time and dedication of resources required to perform traditional routing iterations. Route-planning allows package design teams to easily communicate with customers and other engineering teams to make intelligent trade-off decisions for layer usage, space allocation, Power Delivery Network (PDN) solutions, signal referencing and Die-to-Pkg netlist feasibility and optimization.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000720-000728
Author(s):  
Jorge Teixeira ◽  
Mário Ribeiro

Wafer level packaging is an important development trend for IC package design. One of the emerging variants is the fan-out wafer level package (FO-WLP), namely Embedded Wafer Level Ball Array (eWLB) [1]. In the eWLB process, singulated known good dies are placed into a “reconstituted wafer” with enough space around each chip to accommodate second-level connections. Space between dies is filled with molding compound, this construction results in a plurality of microelectronic elements triggering a particular mechanical behavior.[1]. Two of the main characteristics associated to the handling and process capabilities of wafers are warpage (or bow) and stiffness. These two properties are directly related to the success of the wafer handling and processing. However, all equipment and processes running FO-WLP were designed to process silicon wafers, which have high and homogenous rigidity and whose behavior approaches that of a true elastic material, in opposition to the “reconstituted wafer”. This fact poses several manufacturing and process challenges when dealing with “reconstituted wafers”. Currently, different warpage methods and measurement systems are available, but wafer stiffness assessment is not yet explored and to our knowledge there is no commercially available instrument to perform this task. In our research, it's presented an original experimental method to measure wafer stiffness. The method is based on an apparatus specifically designed to quickly record the force-displacement curve of wafer stiffness. Results are demonstrated by varying different characteristics of reconstituted wafers: Si/mold compound ratio, wafer thickness, mold compound, humidity absorption and process steps. The correlation between wafer stiffness and warpage was also investigated. This method has been successfully used in the field and showed to be a valuable process instrument for both product development and process monitoring.


Author(s):  
Thomas M. Moore

In the last decade, a variety of characterization techniques based on acoustic phenomena have come into widespread use. Characteristics of matter waves such as their ability to penetrate optically opaque solids and produce image contrast based on acoustic impedance differences have made these techniques attractive to semiconductor and integrated circuit (IC) packaging researchers.These techniques can be divided into two groups. The first group includes techniques primarily applied to IC package inspection which take advantage of the ability of ultrasound to penetrate deeply and nondestructively through optically opaque solids. C-mode Acoustic Microscopy (C-AM) is a recently developed hybrid technique which combines the narrow-band pulse-echo piezotransducers of conventional C-scan recording with the precision scanning and sophisticated signal analysis capabilities normally associated with the high frequency Scanning Acoustic Microscope (SAM). A single piezotransducer is scanned over the sample and both transmits acoustic pulses into the sample and receives acoustic echo signals from the sample.


Author(s):  
Daniel Nuez ◽  
Phoumra Tan

Abstract Conductive anodic filament (CAF) formation is a mechanism caused by an electrochemical migration of metals from a metal trace in ICs or in PCBs. This is commonly caused by the moisture build-up in the affected metal terminals in an IC package or PC board caused by critical temperature, high humidity and high voltage gradients conditions. This phenomenon is known to have caused catastrophic field failures on various OEMs electronic components in the past [1,7]. Most published articles on CAF described the formation of the filament in a lateral formation through the glass fiber interfaces between two adjacent metal planes [1-6, 8-12]. One common example is the CAF formation seen between PTH (Plated through Hole) in the laminated substrate with two different potentials causing shorts [1-6, 8-12]. In this paper, the Cu filament grows in a vertical fashion (z-axis formation) creating a vertical plane shorts between the upper and lower metal terminals in a laminated IC package substrate. The copper growth migration does not follow the fiber strands laterally or vertically through them. Instead, it grows through the stress created gaps between the impregnated carbon epoxy fillers from the upper metal trace to the lower metal trace with two different potentials, between the glass fibers. This vertical CAF mechanism creates a low resistive short that was sometimes found to be intermittent in nature. This paper presents some successful failure analysis approaches used to isolate and detect the failure locations for this type of failing devices. This paper also exposes the unique physical appearance of the vertical CAF formation.


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