Study on Distortion Characteristics of Analog Circuit by Nonlinear Degree of Integrated Circuit Amplifier

2019 ◽  
pp. 1274-1279
Author(s):  
Wang Tao ◽  
Sun Wen
Keyword(s):  
Integrated Circuit ◽  
Analog Circuit

Analog Circuit Failure Analysis Using Time-Resolved Emission

2005 ◽  
Author(s):  
B.J. Cain ◽  
G.L. Woods ◽  
A. Syed ◽  
R. Herlein ◽  
Toshihiro Nomura
Keyword(s):  
Analog Circuits ◽  
Integrated Circuit ◽  
Analog Circuit ◽  
Photon Emission ◽  
Nonlinear Process ◽  
Time Resolved ◽  
Non Invasive ◽  
Highly Nonlinear ◽  
Excellent Spatial Resolution ◽  
5 Ghz

Abstract Time-Resolved Emission (TRE) is a popular technique for non-invasive acquisition of time-domain waveforms from active nodes through the backside of an integrated circuit. [1] State-of-the art TRE systems offer high bandwidths (> 5 GHz), excellent spatial resolution (0.25um), and complete visibility of all nodes on the chip. TRE waveforms are typically used for detecting incorrect signal levels, race conditions, and/or timing faults with resolution of a few ps. However, extracting the exact voltage behavior from a TRE waveform is usually difficult because dynamic photon emission is a highly nonlinear process. This has limited the perceived utility of TRE in diagnosing analog circuits. In this paper, we demonstrate extraction of voltage waveforms in passing and failing conditions from a small-swing, differential logic circuit. The voltage waveforms obtained were crucial in corroborating a theory for some failures inside an 0.18um ASIC.

A Non-Destructive and Effective Metrology to Automatically Monitor Kink Effect of MOSFETs

2011 ◽  
Vol 291-294 ◽  
pp. 2910-2913
Author(s):  
Mu Chun Wang ◽  
Hsin Chia Yang
Keyword(s):  
Integrated Circuit ◽  
Analog Circuit ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Shallow Trench Isolation ◽  
Kink Effect ◽  
Local Oxidation ◽  
Trench Isolation ◽  
Second Derivative Method ◽  
Non Destructive

The kink effect is a harassed issue existing in metal-oxide-semiconductor field-effect transistors (MOSFETs) and usually degrades the whole chip performance, especially in analog circuit operation. No matter what the device isolation is with local oxidation of silicon (LOCOS) process or shallow trench isolation (STI) process, this effect more or less depicts. How to sense this effect in integrated-circuit (IC) mass-production is a crucial event. Through a second derivative method on Ids versus Vgs curves in MOSFET device, the unhealthy devices can be effectively screened out with the application of programmable auto testers. Using this derivative metrology implemented into the measurement testers, the distribution of kink devices on wafer is easily plotted. This information is very precious to the semiconductor process engineers in process improvement, too.

A Novel Robot Vision Employing a Silicon Retina

2001 ◽  
Vol 13 (6) ◽  
pp. 614-620 ◽  
Author(s):  
Kazuhiro Shimonomura ◽  
◽  
Seiji Kameda ◽  
Kazuo Ishii ◽  
Tetsuya Yagi ◽  
...  
Keyword(s):  
Real Time ◽  
Integrated Circuit ◽  
Large Scale ◽  
Analog Circuit ◽  
Vision System ◽  
Robot Vision ◽  
Illumination Condition ◽  
Output Image ◽  
Analog Cmos ◽  
Silicon Retina

A Robot vision system was designed using a silicon retina, which has been developed to mimick the parallel circuit structure of the vertebrate retina. The silicon retina used here is an analog CMOS very large-scale integrated circuit, which executes Laplacian-Gaussian like filtering on the image in real time. The processing is robust to change of illumination condition. Analog circuit modules were designed to detect the contour from the output image of the silicon retina and to binarize the output image. The images processed by the silicon retina as well as those by the analog circuit modules are received by the DOS/V-compatible mother-board with NTSC signal, which enables higher level processings using digital image processing techniques. This novel robot vision system can achieve real time and robust processings in natural illumination condition with a compact hardware and a low power consumption.

A Typical MOSFET Modeling Procedure for RF Analog Circuit Design

2016 ◽  
Vol 698 ◽  
pp. 87-99
Author(s):  
Hitoshi Aoki ◽  
Haruo Kobayashi
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Analog Circuit ◽  
Model Parameters ◽  
Analog Circuit Design ◽  
Integrated Circuit Design ◽  
Test Parameters ◽  
Analog Integrated Circuit Design ◽  
Cascode Amplifier ◽  
Typical Model

This paper presents a theoretical yet practical device targeting method to extract typical model parameters of MOSFET devices on wafer for RF analog integrated circuit design. This method employs skewing algorithms with model parameters of existing typical device which are selected by using inter-lot process electrical test parameters. Although this technique can be applied for both n-channel and p-channel MOSFETs, only n-channel devices could be prepared for our experiments in this research. To demonstrate the plausibility of this method, a cascode amplifier is designed to simulate frequency characteristic of S21 with this method.

Characterization and Modeling of SiC LTJFET for Analog Integrated Circuit Simulation and Design

2009 ◽  
Vol 615-617 ◽  
pp. 915-918 ◽  
Author(s):  
A. Maralani ◽  
Michael S. Mazzola ◽  
David C. Sheridan ◽  
Igor Sankin ◽  
Volodymyr Bondarenko
Keyword(s):  
Integrated Circuits ◽  
Threshold Voltage ◽  
Integrated Circuit ◽  
Analog Circuit ◽  
Circuit Simulation ◽  
Analog Integrated Circuits ◽  
Effect Of Temperature ◽  
Common Source ◽  
Small Signal ◽  
Signal Parameters

The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal parameters are reported, (3) gain performance and small signal parameters of the basic analog circuit block, Common Source (CS) amplifier, based on the variation of the load transistors threshold voltage (Vth) are studied and analyzed, and (4) frequency and transient response of the cascoded CS amplifier (CS-Cas) are reported.

scholarly journals Wavelet-Based Feature Extraction in Fault Diagnosis for Biquad High-Pass Filter Circuit

2016 ◽  
Vol 2016 ◽  
pp. 1-13 ◽  
Author(s):  
Yuehai Wang ◽  
Yongzheng Yan ◽  
Qinyong Wang
Keyword(s):  
Feature Extraction ◽  
Fault Diagnosis ◽  
Integrated Circuits ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Analog Circuit ◽  
Pass Filter ◽  
Op Amp ◽  
Biquad Filter ◽  
Feature Extraction And Selection

Fault diagnosis for analog circuit has become a prominent factor in improving the reliability of integrated circuit due to its irreplaceability in modern integrated circuits. In fact fault diagnosis based on intelligent algorithms has become a popular research topic as efficient feature extraction and selection are a critical and intricate task in analog fault diagnosis. Further, it is extremely important to propose some general guidelines for the optimal feature extraction and selection. In this paper, based on wavelet analysis, we will study the problems of mother wavelets selection, number of decomposition levels, and candidate coefficients selection by using a four-op-amp biquad filter circuit. After conducting several comparative experiments, some general guidelines for feature extraction for this type of analog circuits fault diagnosis are derived.

Advances in Analog Integrated Circuit Optimization

2018 ◽  
pp. 309-333 ◽  
Author(s):  
Prakash Kumar Rout ◽  
Debiprasad Priyabrata Acharya ◽  
Umakanta Nanda
Keyword(s):  
Process Optimization ◽  
Performance Measures ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Digital Circuits ◽  
Analog Circuit ◽  
Environmental Constraints ◽  
Circuit Optimization ◽  
Circuit Sizing ◽  
Central Task

In a system though the analog circuits occupy very less space but they require far more design time than the digital circuits. This is due to the fact that the number of performance measures of an analog circuit is more than those for digital circuits. Predicting and improving the performance, robustness and overall cost of such systems is a major concern in the process of automation. In the automation process, optimization of performances subjected to a verity of environmental constraints is a central task. In this chapter, efficient analog circuit sizing techniques and their optimization are surveyed.

scholarly journals Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 685 ◽  
Author(s):  
Adriana Sanabria-Borbón ◽  
Sergio Soto-Aguilar ◽  
Johan Estrada-López ◽  
Douglas Allaire ◽  
Edgar Sánchez-Sinencio
Keyword(s):  
Gaussian Process ◽  
Integrated Circuit ◽  
Surrogate Model ◽  
Analog Circuit ◽  
Performance Metrics ◽  
Low Cost ◽  
Optimization Algorithms ◽  
Process Variations ◽  
Building Blocks ◽  
Circuit Simulations

Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is 69 X to 470 X faster at evaluation compared with circuit simulations.

The Precipitation of Si in AlCuSi Thin Films

1973 ◽  
Vol 31 ◽  
pp. 34-35 ◽  
Author(s):  
R. M. Anderson
Keyword(s):  
Electron Microscopy ◽  
Thin Films ◽  
Heat Treatment ◽  
Solid Solution ◽  
Integrated Circuit ◽  
Copper Film ◽  
Solution Concentration ◽  
X Ray ◽  
Silicon Thin Films ◽  
Before And After

Aluminum-copper-silicon thin films have been considered as an interconnection metallurgy for integrated circuit applications. Various schemes have been proposed to incorporate small percent-ages of silicon into films that typically contain two to five percent copper. We undertook a study of the total effect of silicon on the aluminum copper film as revealed by transmission electron microscopy, scanning electron microscopy, x-ray diffraction and ion microprobe techniques as a function of the various deposition methods.X-ray investigations noted a change in solid solution concentration as a function of Si content before and after heat-treatment. The amount of solid solution in the Al increased with heat-treatment for films with ≥2% silicon and decreased for films <2% silicon.

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