A Novel High Speed Dynamic Comparator Using Positive Feedback with Low Power Dissipation and Low Offset

Author(s):  
Silpakesav Velagaleti ◽  
Pavankumar Gorpuni ◽  
K. K. Mahapatra
2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 11-13
Author(s):  
Truptimayee Behera ◽  
Ritisnigdha Das

In our design of CMOS comparator with high performance using GPDK 180nm technology we optimize these parameters. We analyse the transient response of the schematic design and the gain is calculated in AC analysis and also we measure the power dissipation. The circuit is built by using PMOS and NMOS transistor with a body effect. A plot of phase and gain also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 2V is measured using Cadence virtuoso. Simulation results are presented and it shows that this design can work under high speed clock frequency 200MHz. The design has low power dissipation.


Author(s):  
Lobna Osman ◽  

Motivated by the merits of low power dissipation, ultra-small size, and high speed of many nanoelectronic devices, They have been demonstrated to ensure future progress. Single-electron devices became one of the most important nanoelectronic devices due to their interesting electrical characteristics and behavior. Many research efforts moved to describe their electrical characteristics to use them with conventional electronic devices. This paper deals with modeling and simulation of such new electronic devices. This paper presents a model for the Single Electron Transistor (SET) and its application in simulating hybrid SET/MOS ADC and DAC converters. This model uses the orthodox theory of single-electron tunneling and determines the average current through the transistor. The proposed model is more flexible that is valid for a large range of drain to source voltage, valid for single or multi-gate SET and symmetric or asymmetric SET. Finally, using this model with MOSFET transistors to realize multi-bit Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC). The hybrid n-bit DAC nano-circuits are simulated for (n=4 and 8) using Orcad Capture PSPICE. The performance of the SET/MOS hybrid n-bit ADC circuits were simulated (for n=3 and 8). The results show that the transient operation of hybrid SET/MOS circuit-based DAC could successfully operate at 1000K while ADC could operate at 144K. This performance can be compared with the pure SET circuits, the proposed converter circuits have been enhanced in the drive capability and the power dissipation. Compared with the other SET/MOS hybrid circuit, the implemented converter circuits have low simulation time, high speed, high load drivability, and low power dissipation.


2014 ◽  
Vol 35 (5) ◽  
pp. 055008 ◽  
Author(s):  
Shubin Liu ◽  
Zhangming Zhu ◽  
Yintang Yang ◽  
Lianxi Liu

2005 ◽  
Author(s):  
J. Graul ◽  
H. Kaiser ◽  
N. Kokkotakis ◽  
W. Wilhelm ◽  
H. Ryssel ◽  
...  

2013 ◽  
Vol 321-324 ◽  
pp. 2822-2827 ◽  
Author(s):  
Mao Qiang Duan ◽  
Xiao Li Huang

The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.


Low power consumption, high performance dynamic comparators are widely used in high-speed Analog to Digital Converters (ADCs) and advanced input/output circuits. Mostly unique comparators utilize the latching stage thorough cross-coupled inverters, which gives a solid positive feedback, to fasten the comparison and reduce the static- power dissipation. In this paper, the analysis of dynamic comparators having best performance parameters in terms of power dissipation is presented. This is achieved by adopting low power techniques like adding transistors and sizing them to get efficient circuit. The proposed circuits are able to reduce power dissipation from 40-50%


2013 ◽  
Vol 52 (1) ◽  
pp. 105-109 ◽  
Author(s):  
X. Tong ◽  
H. Wu ◽  
L. Zhao ◽  
H. Zhong

Author(s):  
A. Satoh ◽  
Y. Kobayashi ◽  
H. Niijima ◽  
N. Ooba ◽  
S. Munetoh ◽  
...  

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