Design of Energy-Efficient Random Access Memory Circuit Using Low-Voltage CMOS and High-Speed Transreceiver Logic-I I/O Standard on 28 nm FPGA

2018 ◽  
pp. 95-106
Author(s):  
Tarun Agrawal ◽  
Vivek Srivastava
Keyword(s):  
Energy Efficient ◽  
High Speed ◽  
Low Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Memory Circuit ◽  
28 Nm

scholarly journals Challenges and Applications of Emerging Nonvolatile Memory Devices

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1029 ◽  
Author(s):  
Writam Banerjee
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Random Access ◽  
Random Access Memory ◽  
Spin Transfer Torque ◽  
High Density ◽  
Memory Storage ◽  
Access Memory ◽  
Ultra Low Power

Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

An energy efficient and high speed architecture for convolution computing based on binary resistive random access memory

2018 ◽  
Vol 57 (4S) ◽  
pp. 04FE05
Author(s):  
Chen Liu ◽  
Runze Han ◽  
Zheng Zhou ◽  
Peng Huang ◽  
Lifeng Liu ◽  
...  
Keyword(s):  
Energy Efficient ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory

Silicon stacked tunnel transistor for high-speed and high-density random access memory gain cells

1999 ◽  
Vol 35 (10) ◽  
pp. 848 ◽  
Author(s):  
K. Nakazato ◽  
K. Itoh ◽  
H. Mizuta ◽  
H. Ahmed
Keyword(s):  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
High Density ◽  
Access Memory ◽  
Tunnel Transistor

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

Design of all-dc-powered high-speed single flux quantum random access memory based on a pipeline structure for memory cell arrays

2006 ◽  
Vol 19 (5) ◽  
pp. S325-S330 ◽  
Author(s):  
Shuichi Nagasawa ◽  
Kenji Hinode ◽  
Tetsuro Satoh ◽  
Yoshihiro Kitagawa ◽  
Mutsuo Hidaka
Keyword(s):  
High Speed ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Flux Quantum ◽  
Access Memory ◽  
Cell Arrays

Nonvolatile Magnetoresistive Random-Access Memory Based on Magnetic Tunnel Junctions

MRS Bulletin ◽  
2004 ◽  
Vol 29 (11) ◽  
pp. 818-821 ◽  
Author(s):  
G. Grynkewich ◽  
J. Åkerman ◽  
P. Brown ◽  
B. Butcher ◽  
R.W. Dave ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Magnetoresistive Random Access Memory ◽  
Static Ram ◽  
New Memory Technology

AbstractMagnetoresistive random-access memory (MRAM) is a new memory technology that is nearing commercialization. MRAM integrates a magnetic tunnel junction (MTJ) device with standard silicon-based microelectronics, resulting in a combination of qualities not found in other memory technologies. For example, MRAM is nonvolatile, has unlimited read and write endurance, and is capable of high-speed read and write operations. In this article, we will describe the fundamentals of an MTJ-based MRAM as well as recent important technology developments in the areas of magnetic materials and memory cell architecture. In addition, we will compare the present and future capabilities of MRAM to those of existing memory technologies such as static RAM and flash memory.

A 4096-bit high-speed emitter-coupled-logic (ECL) compatible random-access memory

1975 ◽  
Vol 10 (5) ◽  
pp. 262-267 ◽  
Author(s):  
M.S. Ebel ◽  
J. Gionis ◽  
W.M. Regitz
Keyword(s):  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory
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