UPM-NoC: Learning Based Framework to Predict Performance Parameters of Mesh Architecture in On-Chip Networks

2019 ◽  
pp. 723-733
Author(s):  
Anil Kumar ◽  
Basavaraj Talawar
Keyword(s):  
Performance Parameters ◽  
Mesh Architecture ◽  
On Chip

scholarly journals A high-throughput network on-chip in full-mesh architecture

2018 ◽  
Vol 15 (17) ◽  
pp. 20180635-20180635
Author(s):  
Hongyu Meng ◽  
Lei Yang ◽  
Zijun Liu ◽  
Donglin Wang
Keyword(s):  
High Throughput ◽  
Network On Chip ◽  
Mesh Architecture ◽  
On Chip

scholarly journals Eight Element Side Edged Framed MIMO Antenna Array for Future 5G Smart Phones

Micromachines ◽  
2020 ◽  
Vol 11 (11) ◽  
pp. 956 ◽  
Author(s):  
Saad Hassan Kiani ◽  
Ahsan Altaf ◽  
Mujeeb Abdullah ◽  
Fazal Muhammad ◽  
Nosherwan Shoaib ◽  
...  
Keyword(s):  
Liquid Crystal Display ◽  
Multiple Input Multiple Output ◽  
Cost Effective ◽  
Antenna System ◽  
Human Hand ◽  
Single Element ◽  
Performance Parameters ◽  
Mimo Antenna ◽  
Principal Performance ◽  
On Chip

This paper presents a novel design of a Multiple Input Multiple Output (MIMO) antenna system for next generation sub 6 GHz 5G and beyond mobile terminals. The proposed system is composed of a main board and two side boards. To make the design cost-effective, FR4 is used as a substrate. The design is based on a unit monopole antenna etched at the side substrate. The single element is resonating at 3.5 GHz attaining a 10 dB bandwidth of 200 MHz and a 6 dB bandwidth of 400 MHz. The single element is then transformed into an MIMO array of 8-elements with an overall dimension of 150 mm × 75 mm × 7 mm, providing pattern diversity characteristics and isolation better than −12 dB for any two radiating elements. A number of studies such as effects of human hand on the system that includes single hand mode and dual mode scenarios and the effects of Liquid Crystal Display (LCD) over the principal performance parameters of the system are presented. The envelop correlation coefficient (ECC) is computed for all the scenarios and it is found that ECC is less than 0.1 for any case and maximum channel capacity is 38.5 bps/Hz within the band of interest. The main advantage of the proposed design over available designs in the literature is that almost all of the main substrate is empty providing wide space for different sensors, systems, and mobile technology components. A brief literature comparison of the proposed system is also presented. To validate the proposed model, a prototype is fabricated and results are presented. This design can be applied on higher frequencies to future micromachines for on chip communications using same theocratical approach as the space for higher frequencies in mmwave spectrum has been reserved. The simulated results are in an excellent agreement with the measured results. All the main performance parameters of the design are calculated and compared with the measured results wherever possible.

scholarly journals Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

2021 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Narendra Kumar Garg ◽  
Vivek Singh Kushwah ◽  
Manisha Pattanaik
Keyword(s):  
Digital Circuits ◽  
Leakage Power ◽  
Performance Parameters ◽  
New Techniques ◽  
Vlsi Interconnects ◽  
Digital Electronics ◽  
Spice Model ◽  
On Chip ◽  
Carbon Nano Tube ◽  
The Impact

Abstract With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.

Implementation of a High-Precision pH Sensor

2013 ◽  
Vol 373-375 ◽  
pp. 358-362
Author(s):  
Zhan Wei Xu ◽  
Gui Lin Zheng
Keyword(s):  
High Precision ◽  
Measurement Accuracy ◽  
Ph Sensor ◽  
Operational Amplifiers ◽  
Full Description ◽  
Performance Parameters ◽  
Ad Converter ◽  
On Chip ◽  
The Impact ◽  
Wire Resistance

A high-precision pH sensor based on electrochemical principle is proposed in the paper. The principle of the sensor, the performance parameters of MCU, hardware architecture and experiment are introduced. The NEC microprocessor, which is low-power and high stability, is adopted as core processor. The three operational amplifiers same-phase parallel amplifying circuit not only matches the impendence of the pH combination electrode, but also eliminates the impact of wire resistance on pH measurement. The system's capacity of resisting disturbance is improved. Using 18-bit AD converter, which has programmable amplifier on chip, improves measurement accuracy. Both theoretical analysis and experimental results show the effectiveness of the pH sensor. A full description of the pH sensor and implementation are presented.

Macro and Micro Architectures for Network on Chip

2021 ◽  
pp. 44-74
Author(s):  
P. Suresh
Keyword(s):  
Computer Network ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
System Level ◽  
Comparison Result ◽  
New Concepts ◽  
Different Dimensions ◽  
Mesh Architecture ◽  
On Chip

Network on chip (NoC) paradigm replaces traditional, dedicated, and proprietary bus architectures of system on chip (SoC), and it is widely accepted by the system-level designers. In this chapter, an overview of the NoC design is presented in two different dimensions called macro-architectures and micro-architectures based on the design perspectives. Macro-architectures adopt the concept of computer network along with new innovations in topologies, protocols, and routing algorithms and so on whereas micro-architectures involve in the development of schedulers, arbiters, routers, and network adapter with existing or new concepts. From the comparison result, most of the NoC prototypes are developed with 2-D mesh architecture with packed switched concept. Apart from mesh architectures, some of the complex and hybrid concepts are also developed and discussed in this chapter.

scholarly journals Optimization Simulation programming for NoC

2019 ◽  
pp. 13-18
Author(s):  
Dhafer Sabah Yaseen
Keyword(s):  
Software Tool ◽  
Multiprocessor Systems ◽  
Performance Parameters ◽  
Promising Alternative ◽  
Networks On Chip ◽  
Communication Links ◽  
Optimization Simulation ◽  
On Chip ◽  
Ip Blocks ◽  
Bus Architecture

The article presents the concept of networks-on-chip (NoCs) as a promising alternative to communication subsystem for multiprocessor systems with bus architecture. The networks simulator developed as important software tool to estimate NoC performance parameters. The results of approbation of the developed simulator are reliance of the number of hops on the NoC dimension for mesh and torus topologies, as well as the dependences of communication links workload on the frequency, with which IP blocks generate messages. Its possibilities are considered and the accepted results are given.

scholarly journals Development of a software simulator of networks on a chip

2011 ◽  
Vol 16 (4) ◽  
pp. 48-52
Author(s):  
D.A. Fes'kov ◽  
A.YU. Romanov
Keyword(s):  
Software Tool ◽  
Multiprocessor Systems ◽  
Performance Parameters ◽  
Promising Alternative ◽  
Networks On Chip ◽  
On Chip ◽  
Bus Architecture

The article presents the concept of networks-on-chip (NoC) as a promising alternative to communication subsystem for multiprocessor systems with bus architecture. The networks simulator developed as a necessary software tool to evaluate NoC performance parameters. Its possibilities are considered and the results of its approbation are given

ОСОБЕННОСТИ ПРОЕКТИРОВАНИЯ СБОЕУСТОЙЧИВЫХ СВЕРХБЫСТРОДЕЙСТВУЮЩИХ ЛОГИЧЕСКИХ ЦЕПЕЙ КМОП СБИС СНК

2020 ◽  
Vol 96 (3s) ◽  
pp. 220-228
Author(s):  
Ю.М. Герасимов ◽  
Н.Г. Григорьев ◽  
А.В. Кобыляцкий ◽  
Я.Я. Петричкович ◽  
Д.К. Сергеев
Keyword(s):  
High Speed ◽  
Heavy Ion ◽  
Logic Circuits ◽  
Vlsi Circuit ◽  
Performance Parameters ◽  
Asymptotic Performance ◽  
Clock Frequency ◽  
Nanometer Cmos ◽  
Nuclear Particle ◽  
On Chip

Проанализированы асимптотические параметры быстродействия нанометровых (суб-100 нм) КМОП-технологий объемного кремния (ОК) уровня 90-28 нм. Показано, что сбоеустойчивость логических цепей при воздействии отдельных ядерных частиц (ОЯЧ) зависит от частоты синхронизации СБИС и ухудшается при ее повышении. Даны рекомендации по проектированию сбоеустойчивых быстродействующих логических цепей в составе СБИС типа «система на кристалле» (СнК). The paper deals with asymptotic performance parameters of nanometer-CMOS technologies at a level of90-28 nm. It is shown that the single nuclear particle tolerance of logical circuits depends on the clock frequency of the VLSI circuit and worsens with its increase. Recommendations are given on the design of heavy-ion tolerant high-speed logic circuits in the system-on-chip (SoC) type VLSI.

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