ОСОБЕННОСТИ ПРОЕКТИРОВАНИЯ СБОЕУСТОЙЧИВЫХ СВЕРХБЫСТРОДЕЙСТВУЮЩИХ ЛОГИЧЕСКИХ ЦЕПЕЙ КМОП СБИС СНК

2020 ◽  
Vol 96 (3s) ◽  
pp. 220-228
Author(s):  
Ю.М. Герасимов ◽  
Н.Г. Григорьев ◽  
А.В. Кобыляцкий ◽  
Я.Я. Петричкович ◽  
Д.К. Сергеев
Keyword(s):  
High Speed ◽  
Heavy Ion ◽  
Logic Circuits ◽  
Vlsi Circuit ◽  
Performance Parameters ◽  
Asymptotic Performance ◽  
Clock Frequency ◽  
Nanometer Cmos ◽  
Nuclear Particle ◽  
On Chip

Проанализированы асимптотические параметры быстродействия нанометровых (суб-100 нм) КМОП-технологий объемного кремния (ОК) уровня 90-28 нм. Показано, что сбоеустойчивость логических цепей при воздействии отдельных ядерных частиц (ОЯЧ) зависит от частоты синхронизации СБИС и ухудшается при ее повышении. Даны рекомендации по проектированию сбоеустойчивых быстродействующих логических цепей в составе СБИС типа «система на кристалле» (СнК). The paper deals with asymptotic performance parameters of nanometer-CMOS technologies at a level of90-28 nm. It is shown that the single nuclear particle tolerance of logical circuits depends on the clock frequency of the VLSI circuit and worsens with its increase. Recommendations are given on the design of heavy-ion tolerant high-speed logic circuits in the system-on-chip (SoC) type VLSI.

scholarly journals A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4715
Author(s):  
Wei He ◽  
Jinguo Huang ◽  
Tengxiao Wang ◽  
Yingcheng Lin ◽  
Junxian He ◽  
...  
Keyword(s):  
Online Learning ◽  
High Speed ◽  
Low Cost ◽  
High Energy ◽  
Training Procedure ◽  
Vision Sensor ◽  
Clock Frequency ◽  
Dynamic Vision ◽  
Vlsi System ◽  
On Chip

This paper proposes a high-speed low-cost VLSI system capable of on-chip online learning for classifying address-event representation (AER) streams from dynamic vision sensor (DVS) retina chips. The proposed system executes a lightweight statistic algorithm based on simple binary features extracted from AER streams and a Random Ferns classifier to classify these features. The proposed system’s characteristics of multi-level pipelines and parallel processing circuits achieves a high throughput up to 1 spike event per clock cycle for AER data processing. Thanks to the nature of the lightweight algorithm, our hardware system is realized in a low-cost memory-centric paradigm. In addition, the system is capable of on-chip online learning to flexibly adapt to different in-situ application scenarios. The extra overheads for on-chip learning in terms of time and resource consumption are quite low, as the training procedure of the Random Ferns is quite simple, requiring few auxiliary learning circuits. An FPGA prototype of the proposed VLSI system was implemented with 9.5~96.7% memory consumption and <11% computational and logic resources on a Xilinx Zynq-7045 chip platform. It was running at a clock frequency of 100 MHz and achieved a peak processing throughput up to 100 Meps (Mega events per second), with an estimated power consumption of 690 mW leading to a high energy efficiency of 145 Meps/W or 145 event/μJ. We tested the prototype system on MNIST-DVS, Poker-DVS, and Posture-DVS datasets, and obtained classification accuracies of 77.9%, 99.4% and 99.3%, respectively. Compared to prior works, our VLSI system achieves higher processing speeds, higher computing efficiency, comparable accuracy, and lower resource costs.

Design of a SoC With High-Speed DDC for Software Radio Receiver

2012 ◽  
Vol 605-607 ◽  
pp. 1875-1879 ◽  
Author(s):  
Jun Deng ◽  
Lin Tao Liu ◽  
Yu Jing Li ◽  
Xiao Zong Huang ◽  
Xu Huang ◽  
...  
Keyword(s):  
High Speed ◽  
Software Radio ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
Radio Receiver ◽  
Clock Frequency ◽  
Baseband Signal ◽  
Baseband Signal Processing ◽  
Good Potential ◽  
On Chip

This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

1999 ◽  
Vol 6 (10-12) ◽  
pp. 823-828 ◽  
Author(s):  
Y Hashimoto ◽  
S Yorozu ◽  
H Numata ◽  
M Koike ◽  
M Tanaka ◽  
...  
Keyword(s):  
High Speed ◽  
Pattern Generator ◽  
Logic Circuits ◽  
Signal Pattern ◽  
On Chip ◽  
Chip Signal

Design of a high speed router for NOC

2021 ◽  
pp. 2140012
Author(s):  
Zhanpeng Jiang ◽  
Zhe Yang ◽  
Penghui Zhang ◽  
Changchun Dong
Keyword(s):  
High Speed ◽  
Control Mechanism ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Performance Parameters ◽  
Wormhole Switching ◽  
Deterministic Routing ◽  
On Chip ◽  
Selection Of ◽  
Significant Point

The complexity of System on Chip (SoC) is increasing with the scale of ICs, and Network on Chip (NoC) has become one of the most important solutions for SoC communication. As a significant point of NoC, research of routers and routing algorithms is receiving more and more attention from researchers and research institutes. This paper proposes a high-speed router on-chip router, which adopts wormhole switching mechanism, output queuing caching strategy, Credit-based flow control mechanism and Round-Robin arbitration mechanism, and the entire operation of the router is a two-stage flow. The selection of adaptive and deterministic routing algorithms can be done automatically, and finally, the performance parameters are evaluated.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Prognostic Assessment of the Performance Parameters for the Industrial Diesel Engines Operated with Microalgae Oil

2021 ◽  
Vol 13 (11) ◽  
pp. 6482
Author(s):  
Sergejus Lebedevas ◽  
Laurencas Raslavičius
Keyword(s):  
Energy Efficiency ◽  
Diesel Engine ◽  
High Speed ◽  
Performance Parameters ◽  
Prognostic Assessment ◽  
High Speed Diesel ◽  
Microalgae Oil ◽  
The Difference ◽  
Smoke Opacity ◽  
Efficiency Indicators

A study conducted on the high-speed diesel engine (bore/stroke: 79.5/95.5 mm; 66 kW) running with microalgae oil (MAO100) and diesel fuel (D100) showed that, based on Wibe parameters (m and φz), the difference in numerical values of combustion characteristics was ~10% and, in turn, resulted in close energy efficiency indicators (ηi) for both fuels and the possibility to enhance the NOx-smoke opacity trade-off. A comparative analysis by mathematical modeling of energy and traction characteristics for the universal multi-purpose diesel engine CAT 3512B HB-SC (1200 kW, 1800 min−1) confirmed the earlier assumption: at the regimes of external speed characteristics, the difference in Pme and ηi for MAO100 and D100 did not exceeded 0.7–2.0% and 2–4%, respectively. With the refinement and development of the interim concept, the model led to the prognostic evaluation of the suitability of MAO100 as fuel for the FPT Industrial Cursor 13 engine (353 kW, 6-cylinders, common-rail) family. For the selected value of the indicated efficiency ηi = 0.48–0.49, two different combinations of φz and m parameters (φz = 60–70 degCA, m = 0.5 and φz = 60 degCA, m = 1) may be practically realized to achieve the desirable level of maximum combustion pressure Pmax = 130–150 bar (at α~2.0). When switching from diesel to MAO100, it is expected that the ηi will drop by 2–3%, however, an existing reserve in Pmax that comprises 5–7% will open up room for further optimization of energy efficiency and emission indicators.

scholarly journals On-chip trans-dimensional plasmonic router

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3357-3365 ◽  
Author(s):  
Shaohua Dong ◽  
Qing Zhang ◽  
Guangtao Cao ◽  
Jincheng Ni ◽  
Ting Shi ◽  
...  
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Incident Angle ◽  
Reciprocal Lattice ◽  
Plasmonic Waveguide ◽  
Optical Diffraction ◽  
Local Dynamic ◽  
Phase Gradient ◽  
On Chip ◽  
Plasmon Polaritons

AbstractPlasmons, as emerging optical diffraction-unlimited information carriers, promise the high-capacity, high-speed, and integrated photonic chips. The on-chip precise manipulations of plasmon in an arbitrary platform, whether two-dimensional (2D) or one-dimensional (1D), appears demanding but non-trivial. Here, we proposed a meta-wall, consisting of specifically designed meta-atoms, that allows the high-efficiency transformation of propagating plasmon polaritons from 2D platforms to 1D plasmonic waveguides, forming the trans-dimensional plasmonic routers. The mechanism to compensate the momentum transformation in the router can be traced via a local dynamic phase gradient of the meta-atom and reciprocal lattice vector. To demonstrate such a scheme, a directional router based on phase-gradient meta-wall is designed to couple 2D SPP to a 1D plasmonic waveguide, while a unidirectional router based on grating metawall is designed to route 2D SPP to the arbitrarily desired direction along the 1D plasmonic waveguide by changing the incident angle of 2D SPP. The on-chip routers of trans-dimensional SPP demonstrated here provide a flexible tool to manipulate propagation of surface plasmon polaritons (SPPs) and may pave the way for designing integrated plasmonic network and devices.

scholarly journals Implementation analysis of IoT-based offloading frameworks on cloud/edge computing for sensor generated big data

2021 ◽  
Author(s):  
Karan Bajaj ◽  
Bhisham Sharma ◽  
Raman Singh
Keyword(s):  
High Speed ◽  
Smart Cities ◽  
Fog Computing ◽  
Edge Computing ◽  
Computation Offloading ◽  
Performance Parameters ◽  
Iot Applications ◽  
Time Sensitivity ◽  
Implementation Analysis ◽  
Increasing Demand

AbstractThe Internet of Things (IoT) applications and services are increasingly becoming a part of daily life; from smart homes to smart cities, industry, agriculture, it is penetrating practically in every domain. Data collected over the IoT applications, mostly through the sensors connected over the devices, and with the increasing demand, it is not possible to process all the data on the devices itself. The data collected by the device sensors are in vast amount and require high-speed computation and processing, which demand advanced resources. Various applications and services that are crucial require meeting multiple performance parameters like time-sensitivity and energy efficiency, computation offloading framework comes into play to meet these performance parameters and extreme computation requirements. Computation or data offloading tasks to nearby devices or the fog or cloud structure can aid in achieving the resource requirements of IoT applications. In this paper, the role of context or situation to perform the offloading is studied and drawn to a conclusion, that to meet the performance requirements of IoT enabled services, context-based offloading can play a crucial role. Some of the existing frameworks EMCO, MobiCOP-IoT, Autonomic Management Framework, CSOS, Fog Computing Framework, based on their novelty and optimum performance are taken for implementation analysis and compared with the MAUI, AnyRun Computing (ARC), AutoScaler, Edge computing and Context-Sensitive Model for Offloading System (CoSMOS) frameworks. Based on the study of drawn results and limitations of the existing frameworks, future directions under offloading scenarios are discussed.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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