A high-speed latched comparator with low offset voltage and low dissipation

2012 ◽  
Vol 74 (2) ◽  
pp. 467-471 ◽  
Author(s):  
Zhangming Zhu ◽  
Guangwen Yu ◽  
Hongbing Wu ◽  
Yifei Zhang ◽  
Yintang Yang
Keyword(s):  
High Speed ◽  
Offset Voltage ◽  
Low Dissipation ◽  
Latched Comparator ◽  
Low Offset

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

scholarly journals A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator

2019 ◽  
Vol 9 (1S5) ◽  
pp. 41-44
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Delay Cell ◽  
Offset Voltage ◽  
Static Power ◽  
Cell Sample ◽  
Low Offset

Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5- bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5- bit ADC operates voltage at 1.8 volts and consumes an average power.

A 8GHz Differential Comparator for Ultra High Speed ADC in 90nm CMOS Technology

2014 ◽  
Vol 513-517 ◽  
pp. 4572-4575
Author(s):  
Zhong Ying Zhu ◽  
Hui Hong ◽  
Shi Liang Li
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Analog To Digital ◽  
Fully Differential ◽  
Offset Voltage ◽  
High Speed Adc ◽  
Sine Signal ◽  
Low Offset

A high speed, low offset fully differential comparator for high-speed analog-to-digital converter which can work at a sampling rate of 8GS/s is presented in this paper. The three-stage pre-amplifiers in the improved comparator structure is proposed to ameliorate its gain. The positive feedback regeneration circuit and the improved output buffer are used to ameliorate the comparator bandwidth. Operating with an input sine signal of 1GHz frequency, the circuit can oversample up to 8GS/s with 5bits of resolution. The simulated offset voltage of the comparator by Monte Carlo at 8GHz clock is 5.09mV.

scholarly journals Implementation of Double Tail Dynamic Latched Architecture for High Speed ADC

2019 ◽  
Vol 8 (3) ◽  
pp. 5966-5970
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Total Power ◽  
Silicon Area ◽  
Offset Voltage ◽  
Saturation Region ◽  
Total Power Consumption ◽  
Low Offset ◽  
Portable Communication

In this proposed work, a low offset voltage (mV) and high speed voltage comparator circuit is designed and simulated. With the unceasing rise of various wireless portable communication systems, high speed transceiver circuits, and high speed memory circuit design, sensitized sensor technologies, and wireless sensor network design, the design of high speed, low offset voltage and low power operated comparators are indispensable blocks in the design of a very good analog to digital converter architecture. The proposed work does not entail the usage of any pre-amplification stages, which accounts for the direct reduction of current consumption and silicon area. The MOSFETs at the input differential pair stage of the CMOS comparator circuit are designed to operate in near sub-threshold region rather than in saturation region to account for the low power consumption. The proposed double tail dynamic latched comparator in this work is implemented in 90μm CMOS technology with the operating power supply voltage (VDD) of 1.2 V and sampling frequency of 600 MHz using Microwind EDA tool. The simulated results indicate that the total power consumption is calculated to be of the order of 126.3μw with the delay of 876ps. From the obtained results, the proposed double tail dynamic latched circuit has considerably lowered both the propagation delay time and power consumption, when compared to the previous works.

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