scholarly journals A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator

2019 ◽  
Vol 9 (1S5) ◽  
pp. 41-44
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Delay Cell ◽  
Offset Voltage ◽  
Static Power ◽  
Cell Sample ◽  
Low Offset

Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5- bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5- bit ADC operates voltage at 1.8 volts and consumes an average power.

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

A Novel Pre-Amplifier for DTH in Folding and Interpolating ADC

2013 ◽  
Vol 321-324 ◽  
pp. 367-371
Author(s):  
Jing Lei Han ◽  
Wen Lian Zhang ◽  
Zhi Biao Shao
Keyword(s):  
Power Dissipation ◽  
Software Defined Radio ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Device Mismatch ◽  
Offset Voltage ◽  
Gain Error ◽  
Input Range

A pre-amplifier for distributed track and hold (DTH) circuit in high speed and high resolution folding and interpolating analog-to-digital converter (ADC) is proposed. This scheme resolves several limitations of conventional differential difference pre-amplifier (DDPA) in low voltage supply, compared to the conventional DDPA, the proposed scheme increases the input range so that all DDPAs of DTH can operate effectively, improves the averaging effect of average network, saves the random offset voltage from device mismatch, decreases the gain error of DTH, reduces the output common-mode (CM) deviation of DTH, and enhances the CM rejection of DTH. Based on SMIC 0.18μm CMOS technology and 1.8V power supply, over the input range, results from spectre shows dummy DDPAs of DTH operate effectively, the offset of output CM voltage of DTH decrease to less than 2mV, gain error decrease to less than 1%, the gain of middle novel pre-amplifier and boundary novel pre-amplifier are both 2.5, bandwidths are all above 1.9GHZ, while power dissipation of each DDPA is 3.22mW. The high CM rejection and low gain error decrease the quantification error effectively, and enhance the performance of ADC. The design meets the requirement of ADC applied to software defined radio (SDR).

A 8GHz Differential Comparator for Ultra High Speed ADC in 90nm CMOS Technology

2014 ◽  
Vol 513-517 ◽  
pp. 4572-4575
Author(s):  
Zhong Ying Zhu ◽  
Hui Hong ◽  
Shi Liang Li
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Analog To Digital ◽  
Fully Differential ◽  
Offset Voltage ◽  
High Speed Adc ◽  
Sine Signal ◽  
Low Offset

A high speed, low offset fully differential comparator for high-speed analog-to-digital converter which can work at a sampling rate of 8GS/s is presented in this paper. The three-stage pre-amplifiers in the improved comparator structure is proposed to ameliorate its gain. The positive feedback regeneration circuit and the improved output buffer are used to ameliorate the comparator bandwidth. Operating with an input sine signal of 1GHz frequency, the circuit can oversample up to 8GS/s with 5bits of resolution. The simulated offset voltage of the comparator by Monte Carlo at 8GHz clock is 5.09mV.

scholarly journals Analysis of Low Power Dynamic Comparator

2020 ◽  
Vol 9 (7) ◽  
pp. 329-332
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Low Power Consumption ◽  
Performance Parameters ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Static Power ◽  
Dynamic Comparators

Low power consumption, high performance dynamic comparators are widely used in high-speed Analog to Digital Converters (ADCs) and advanced input/output circuits. Mostly unique comparators utilize the latching stage thorough cross-coupled inverters, which gives a solid positive feedback, to fasten the comparison and reduce the static- power dissipation. In this paper, the analysis of dynamic comparators having best performance parameters in terms of power dissipation is presented. This is achieved by adopting low power techniques like adding transistors and sizing them to get efficient circuit. The proposed circuits are able to reduce power dissipation from 40-50%

scholarly journals 1.5mW,14.68V/µS-Low Power and High Speed Comparator Design for ADC Applications

2019 ◽  
Vol 8 (6S4) ◽  
pp. 1322-1326
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Analog To Digital Converters ◽  
Slew Rate ◽  
Two Stage ◽  
Analog To Digital ◽  
Low Offset ◽  
Medical Equipments

Advanced medical equipments embedded with the sensors, analog to digital converters (ADC) and other equipment. Gain amplifier and the comparator are key blocks in ADCs improvement. Comparator is the key element in achieving a low offset and high slew ratein the ADCs, in addition power and speed optimizationdesigns are preferred. To achieve high speed and low power a modified architecture of a comparator is introduced. A 5V two stage comparator is designed to meet the specifications as, offset value <8.4mV, power dissipation <1.5mW and slew rate>14.68V/µS. Cadence Virtuoso tools and SCL 0.18 µm technology parameters are used for design. Designed comparator shows improved slew rate and power consumption in comparison with the existing comparators

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

2019 ◽  
Vol 29 (06) ◽  
pp. 2050084
Author(s):  
Daiguo Xu ◽  
Hequan Jiang ◽  
Dongbin Fu ◽  
Xiaoquan Yu ◽  
Shiliu Xu ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Low Noise ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Input Noise ◽  
Clock Feedthrough ◽  
Threshold Voltages ◽  
Coupled Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

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