A 8GHz Differential Comparator for Ultra High Speed ADC in 90nm CMOS Technology

2014 ◽  
Vol 513-517 ◽  
pp. 4572-4575
Author(s):  
Zhong Ying Zhu ◽  
Hui Hong ◽  
Shi Liang Li
Keyword(s):  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Analog To Digital ◽  
Fully Differential ◽  
Offset Voltage ◽  
High Speed Adc ◽  
Sine Signal ◽  
Low Offset

A high speed, low offset fully differential comparator for high-speed analog-to-digital converter which can work at a sampling rate of 8GS/s is presented in this paper. The three-stage pre-amplifiers in the improved comparator structure is proposed to ameliorate its gain. The positive feedback regeneration circuit and the improved output buffer are used to ameliorate the comparator bandwidth. Operating with an input sine signal of 1GHz frequency, the circuit can oversample up to 8GS/s with 5bits of resolution. The simulated offset voltage of the comparator by Monte Carlo at 8GHz clock is 5.09mV.

scholarly journals A 1000 Mhz Low Power and High Speed 8-Bit Flash ADC Architecture using 90nm Cmos Technology

2019 ◽  
Vol 8 (11S) ◽  
pp. 11-19
Keyword(s):  
Comparative Analysis ◽  
High Resolution ◽  
Low Power ◽  
Time Domain ◽  
High Speed ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

The design objective is to implement a Low power, High speed and High resolution Flash ADC with increased sampling rate. To make this possible the blocks of ADC are analyzed. The resistive ladder, comparator block, encoder block are the major modules of flash ADC. Firstly, the comparator block is designed so that it consumes low power. A NMOS latch based, PMOS LATCH based and a Strong ARM Latch based comparators were designed separately. A comparative analysis is made with the comparator designs. Comparators in the design is reduced to half by using time domain interpolation. Then a reference subtraction block is designed to generate the subtraction value of voltages easily and its given as input to comparator. Then a more efficient and low power consuming fat tree encoder is designed. Once all the blocks were ready, a 8 bit Flash Analog to Digital Converter was designed using 90nm CMOS technology and all the parameters such as sampling rate, power consumption, resolution were obtained and compared with other works.

scholarly journals A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator

2019 ◽  
Vol 9 (1S5) ◽  
pp. 41-44
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Average Power ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Delay Cell ◽  
Offset Voltage ◽  
Static Power ◽  
Cell Sample ◽  
Low Offset

Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5- bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5- bit ADC operates voltage at 1.8 volts and consumes an average power.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

2014 ◽  
Vol 1049-1050 ◽  
pp. 687-690
Author(s):  
Yu Han Gao ◽  
Ru Zhang Li ◽  
Dong Bing Fu ◽  
Yong Lu Wang ◽  
Zheng Ping Zhang
Keyword(s):  
High Speed ◽  
Binary Code ◽  
Sampling Rate ◽  
Gray Code ◽  
Cmos Technology ◽  
Careful Consideration ◽  
Analog To Digital ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Error Suppression

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime

2014 ◽  
Vol 13 (01) ◽  
pp. 1450003
Author(s):  
Bhanupriya Bhargava ◽  
Pradeep Kumar Sharma ◽  
Shyam Akashe
Keyword(s):  
High Speed ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Frequency Noise ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Op Amp ◽  
Offset Voltage ◽  
Delta Sigma

In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740051 ◽  
Author(s):  
Yunfeng Hu ◽  
Chao Xiong ◽  
Bin Li
Keyword(s):  
Power Supply ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Area Reduction ◽  
Area Efficient

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

A LOW DISTORTION BOOTSTRAPPED SWITCH FOR 4-BIT MDAC

2013 ◽  
Vol 22 (01) ◽  
pp. 1250074 ◽  
Author(s):  
ZHANGMING ZHU ◽  
GUANGWEN YU ◽  
JINGYU WANG ◽  
YINTANG YANG
Keyword(s):  
Output Voltage ◽  
High Speed ◽  
Dynamic Performance ◽  
Cmos Technology ◽  
Digital Converter ◽  
Analog To Digital ◽  
Low Distortion ◽  
Multiplying Dac ◽  
Bootstrapped Switch ◽  
Switch Circuit

A novel bootstrapped switch scheme with low distortion and high-speed is presented. Transmission gate (TG) switch is used to implement the switch circuit, which results in a reduction in the effect of charge injection during sampling phase and an improved linearity. The parasitic capacitance connected to the top plate of battery capacitor is minimized for higher output voltage. The switch has been simulated in Spectre using an SMIC 0.18 μm CMOS technology at 3.3 V and been applied to a 4-bit multiplying DAC (MDAC) in a 14-bit 100 MS/s pipelined analog-to-digital converter (ADC). The 4-bit MDAC has shown a satisfying dynamic performance.

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

2013 ◽  
Vol 22 (04) ◽  
pp. 1350018 ◽  
Author(s):  
ZHANGMING ZHU ◽  
HONGBING WU ◽  
GUANGWEN YU ◽  
YANHONG LI ◽  
LIANXI LIU ◽  
...  
Keyword(s):  
Monte Carlo Simulation ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Reduction Techniques ◽  
Offset Voltage ◽  
Low Offset

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

A Novel Pre-Amplifier for DTH in Folding and Interpolating ADC

2013 ◽  
Vol 321-324 ◽  
pp. 367-371
Author(s):  
Jing Lei Han ◽  
Wen Lian Zhang ◽  
Zhi Biao Shao
Keyword(s):  
Power Dissipation ◽  
Software Defined Radio ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Device Mismatch ◽  
Offset Voltage ◽  
Gain Error ◽  
Input Range

A pre-amplifier for distributed track and hold (DTH) circuit in high speed and high resolution folding and interpolating analog-to-digital converter (ADC) is proposed. This scheme resolves several limitations of conventional differential difference pre-amplifier (DDPA) in low voltage supply, compared to the conventional DDPA, the proposed scheme increases the input range so that all DDPAs of DTH can operate effectively, improves the averaging effect of average network, saves the random offset voltage from device mismatch, decreases the gain error of DTH, reduces the output common-mode (CM) deviation of DTH, and enhances the CM rejection of DTH. Based on SMIC 0.18μm CMOS technology and 1.8V power supply, over the input range, results from spectre shows dummy DDPAs of DTH operate effectively, the offset of output CM voltage of DTH decrease to less than 2mV, gain error decrease to less than 1%, the gain of middle novel pre-amplifier and boundary novel pre-amplifier are both 2.5, bandwidths are all above 1.9GHZ, while power dissipation of each DDPA is 3.22mW. The high CM rejection and low gain error decrease the quantification error effectively, and enhance the performance of ADC. The design meets the requirement of ADC applied to software defined radio (SDR).

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