Evaluating the Chloride Absorption of Unsaturated Cover-Concrete Using Electrical Measurements

2021 ◽  
Author(s):  
Jaehwan Kim ◽  
Young-Jun You
Keyword(s):  
Electrical Measurements ◽  
Cover Concrete ◽  
Chloride Absorption

CBED study of low-temperature InP grown by gas source MBE

1993 ◽  
Vol 51 ◽  
pp. 810-811
Author(s):  
R. Rajesh ◽  
M.J. Kim ◽  
J.S. Bow ◽  
R.W. Carpenter ◽  
G.N. Maracas
Keyword(s):  
Low Temperature ◽  
Second Phase ◽  
Material System ◽  
Ion Milling ◽  
Electrical Measurements ◽  
Gas Source ◽  
Structural And Electrical Properties ◽  
The One ◽  
Lt Inp ◽  
Gas Source Mbe

In our previous work on MBE grown low temperature (LT) InP, attempts had been made to understand the relationships between the structural and electrical properties of this material system. Electrical measurements had established an enhancement of the resistivity of the phosphorus-rich LT InP layers with annealing under a P2 flux, which was directly correlated with the presence of second-phase particles. Further investigations, however, have revealed the presence of two fundamentally different types of precipitates. The first type are the surface particles, essentially an artefact of argon ion milling and containing mostly pure indium. The second type and the one more important to the study are the dense precipitates in the bulk of the annealed layers. These are phosphorus-rich and are believed to contribute to the improvement in the resistivity of the material.The observation of metallic indium islands solely in the annealed LT layers warranted further study in order to better understand the exact reasons for their formation.

Effect of MCl (M = Na, K) addition on microstructure and electrical conductivity of forsterite

2020 ◽  
Vol 92 (1) ◽  
pp. 10901
Author(s):  
Saloua El Asri ◽  
Hamid Ahamdane ◽  
Lahoucine Hajji ◽  
Mohamed El Hadri ◽  
Moulay Ahmed El Idrissi Raghni ◽  
...  
Keyword(s):  
Heat Treatment ◽  
Electrical Conductivity ◽  
Single Phase ◽  
Sol Gel ◽  
Complex Impedance ◽  
Transmission Spectra ◽  
Electrical Measurements ◽  
Cation Type ◽  
Edx Analyses ◽  
The Fourier Transform

Forsterite single phase powder Mg2SiO4 was synthesized by sol–gel method alongside with heat treatment, using two different cation alkaline salts MCl as mineralizers (M = Na, K) with various mass percentages (2.5, 5, 7.5, and 10 wt.%). In this work, we report on the effect of the cation type and the added amount of used mineralizer on microstructure and electrical conductivity of Mg2SiO4. The formation of forsterite started at 680–740  °C and at 630–700  °C with KCl and NaCl respectively, as shown by TG-DTA and confirmed by XRD. Furthermore, the Fourier transform infrared (FTIR) transmission spectra indicated bands corresponding to vibrations of forsterite structure. The morphology and elemental composition of sintered ceramics were examined by SEM-EDX analyses, while their densities, which were measured by Archimedes method, increased with addition of both alkaline salts. The electrical measurements were performed by Complex Impedance Spectroscopy. The results showed that electrical conductivity increased with the addition of both mineralizers, which was higher for samples prepared with NaCl than those prepared with KCl.

LABORATORY PRACTICE AT THE COURSE SPECIAL METHODS AND MEANS OF ELECTRICAL MEASUREMENTS IN THE CONTEXT OF ERASMUS ALIOT PROJECT

2018 ◽  
Vol 27 (103) ◽  
pp. 273-279
Author(s):  
E. J. Maevskaya, ◽  
◽  
O. О. Topuzanov, ◽  
V. L. Biliaiev, ◽  
S. N. Oginskaya, ◽  
...  
Keyword(s):  
Electrical Measurements ◽  
Laboratory Practice

Silicon Surface Chemical Treatments in Oxide/Nitride Dielectric Stack Properties

2002 ◽  
Vol 716 ◽  
Author(s):  
D. Jacques ◽  
S. Petitdidier ◽  
J.L. Regolini ◽  
K. Barla
Keyword(s):  
Oxygen Content ◽  
Oxide Thickness ◽  
Morphological Data ◽  
Electrical Characteristics ◽  
Electrical Measurements ◽  
Chemical Cleaning ◽  
Force Microscopy ◽  
Chemical Treatments ◽  
Atomic Force ◽  
Interfacial Oxygen

AbstractOxide/Nitride dielectric stack is widely used as the standard dielectric for DRAM capacitors. The influence of the chemical cleaning prior to the stack formation has been studied in this work. As a result, morphological data such as stack surface roughness (Atomic Force Microscopy) and silicon nitride (SiN) incubation time for growth are comparable for all the studied cases on <Si>. However, Tof-SIMS exhibits different oxygen content at the Si/stack interface following the different chemical treatments. Electrical measurements show comparable C-V and I-V results, for the same Equivalent Oxide Thickness (same capacitance at strong accumulation i.e.-3V) while the different studied interfaces bring different interface states density with lower values for higher interfacial oxygen content. For DRAM applications, a clear improvement in electrical characteristics is obtained under low interfacial oxygen content conditions. Results are compared in embedded-DRAM cells for which we developed an industrially compatible dielectric deposition sequence to obtain minimum leakage current with maximum specific capacitance and no particular linking constraints.

Development of High Permeability Core Materials for Embeddable Inductors in Flexible Organic Substrates

2003 ◽  
Vol 769 ◽  
Author(s):  
C. K. Liu ◽  
P. L. Cheng ◽  
S. Y. Y. Leung ◽  
T. W. Law ◽  
D. C. C. Lam
Keyword(s):  
Low Temperature ◽  
Sol Gel ◽  
Circuit Board ◽  
Organic Substrates ◽  
Circuit Boards ◽  
High Permeability ◽  
Electrical Measurements ◽  
Different Temperatures ◽  
Spiral Inductors ◽  
Ceramic Tape

AbstractCapacitors, resistors and inductors are surface mounted components on circuit boards, which occupy up to 70% of the circuit board area. For selected applications, these passives are packaged inside green ceramic tape substrates and sintered at temperatures over 700°C in a co-fired process. These high temperature processes are incompatible with organic substrates, and low temperature processes are needed if passives are to be embedded into organic substrates. A new high permeability dual-phase Nickel Zinc Ferrite (DP NZF) core fabricated using a low temperature sol-gel route was developed for use in embedded inductors in organic substrates. Crystalline NZF powder was added to the sol-gel precursor of NZF. The solution was deposited onto the substrates as thin films and heat-treated at different temperatures. The changes in the microstructures were characterized using XRD and SEM. Results showed that addition of NZF powder induced low temperature transformation of the sol-gel NZF phase to high permeability phase at 250°C, which is approximately 350°C lower than transformation temperature for pure NZF sol gel films. Electrical measurements of DP NZF cored two-layered spiral inductors indicated that the inductance increased by three times compared to inductors without the DP NZF cores. From microstructural observations, the increase is correlated with the changes in microstructural connectivity of the powder phase.

Covalent Atomic Bridges Enable Unidirectional Enhancement of Electronic Transport in Aligned Carbon Nanotubes

2019 ◽  
Author(s):  
Mingguang Chen ◽  
Wangxiang Li ◽  
Anshuman Kumar ◽  
Guanghui Li ◽  
Mikhail Itkis ◽  
...  
Keyword(s):  
Carbon Nanotubes ◽  
Electrical Transport ◽  
Large Scale ◽  
The Novel ◽  
Electrical Measurements ◽  
Metal Atoms ◽  
Aligned Carbon Nanotubes ◽  
Transport Channels ◽  
Walled Carbon Nanotubes ◽  
Bulk Structures

<p>Interconnecting the surfaces of nanomaterials without compromising their outstanding mechanical, thermal, and electronic properties is critical in the design of advanced bulk structures that still preserve the novel properties of their nanoscale constituents. As such, bridging the p-conjugated carbon surfaces of single-walled carbon nanotubes (SWNTs) has special implications in next-generation electronics. This study presents a rational path towards improvement of the electrical transport in aligned semiconducting SWNT films by deposition of metal atoms. The formation of conducting Cr-mediated pathways between the parallel SWNTs increases the transverse (intertube) conductance, while having negligible effect on the parallel (intratube) transport. In contrast, doping with Li has a predominant effect on the intratube electrical transport of aligned SWNT films. Large-scale first-principles calculations of electrical transport on aligned SWNTs show good agreement with the experimental electrical measurements and provide insight into the changes that different metal atoms exert on the density of states near the Fermi level of the SWNTs and the formation of transport channels. </p>

Nanoprobing Applications with Capacitance-Voltage and Pulsed Current-Voltage Measurements for Device Failure Analysis

2015 ◽  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Pulsed Current ◽  
Electrical Measurements ◽  
Device Failure ◽  
Mos Devices ◽  
Atomic Force ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Rising Time

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.

A Novel Integrated Reliability Test System for BEOL TDDB Study

2012 ◽  
Author(s):  
Jifeng Chen ◽  
Peilin Song ◽  
Thomas M. Shaw ◽  
Franco Stellari ◽  
Lynne Gignac ◽  
...  
Keyword(s):  
Preliminary Analysis ◽  
Dielectric Breakdown ◽  
Test System ◽  
Accurate Information ◽  
Reliability Test ◽  
Electrical Measurements ◽  
Time Dependent Dielectric Breakdown ◽  
Microscopy Images ◽  
Insight Into

Abstract In this paper, we propose a new methodology and test system to enable the early detection and precise localization of Time-Dependent-Dielectric-Breakdown (TDDB) occurrence in Back-End-of-Line (BEOL) interconnection. The methodology is implemented as a novel Integrated Reliability Test System (IRTS). In particular, through our methodology and test system, we can easily synchronize electrical measurements and emission microscopy images to gather more accurate information and thereby gain insight into the nature of the defects and their relationship to chip manufacturing steps and materials, so that we can ultimately better engineer these steps for higher reliable systems. The details of our IRTS will be presented along with a case study and preliminary analysis results.

Backside Mechanical Preparation Methodology for Effective Failure Analysis on Small and Non-Exposed Die Paddle Package

2018 ◽  
Author(s):  
Ong Pei Hoon ◽  
Ng Kiong Kay ◽  
Gwee Hoon Yen
Keyword(s):  
Failure Analysis ◽  
Chemical Etching ◽  
Chemical Resistance ◽  
Etching Time ◽  
Lead Frame ◽  
Front Side ◽  
Electrical Measurements ◽  
Mechanical Preparation ◽  
Die Surface ◽  
Copper Lead

Abstract Chemical etching is commonly used in exposing the die surface from die front-side and die backside because of its quick etching time, burr-free and stress-free. However, this technique is risky when performing copper lead frame etching during backside preparation on small and non-exposed die paddle package. The drawback of this technique is that the copper leads will be over etched by 65% Acid Nitric Fuming even though the device’s leads are protected by chemical resistance tape. Consequently, the device is not able to proceed to any other further electrical measurements. Therefore, we introduced mechanical preparation as an alternative solution to replace the existing procedure. With the new method, we are able to ensure the copper leads are intact for the electrical measurements to improve the effectiveness and accuracy of physical failure analysis.

In FAB 300mm Wafer Level Atomic Force Probe Characterization

2012 ◽  
Author(s):  
Terence Kane
Keyword(s):  
Electrical Characterization ◽  
Dark Field ◽  
Wafer Level ◽  
Electrical Measurements ◽  
Manufacturing Line ◽  
Atomic Force ◽  
Monitoring Tools ◽  
Voltage Contrast ◽  
The Cost ◽  
Non Destructive

Abstract A 300mm wafer atomic force prober (AFP) has been installed into IBM’s manufacturing line to enable rapid, nondestructive electrical identification of defects. Prior to this tool many of these defects could not detected until weeks or months later. Moving failure analysis to the FAB provides a means of complementing existing FAB inspection and defect review tools as well as providing independent, non-destructive electrical measurements at an early point in the manufacturing cycle [1] Once the wafer sites are non destructively AFP characterized, the wafer is returned to its front opening unified pod (FOUP) carrier and may be reintroduced into the manufacturing line without disruption for further inspection or processing. Whole wafer atomic force probe electrical characterization has been applied to 32nm, 28nm, 20nm and 14nm node technologies. In this paper we explore the cost benefits of performing non-destructive AFP measurements on whole wafers. We have found the methodology of employing a whole wafer AFP tool complements existing in-line manufacturing monitoring tools such as brightfield/dark field optical inspection, SEM in-line inspection and in-line E-beam voltage contrast inspection (EBI).

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