Backside Mechanical Preparation Methodology for Effective Failure Analysis on Small and Non-Exposed Die Paddle Package

2018 ◽  
Author(s):  
Ong Pei Hoon ◽  
Ng Kiong Kay ◽  
Gwee Hoon Yen
Keyword(s):  
Failure Analysis ◽  
Chemical Etching ◽  
Chemical Resistance ◽  
Etching Time ◽  
Lead Frame ◽  
Front Side ◽  
Electrical Measurements ◽  
Mechanical Preparation ◽  
Die Surface ◽  
Copper Lead

Abstract Chemical etching is commonly used in exposing the die surface from die front-side and die backside because of its quick etching time, burr-free and stress-free. However, this technique is risky when performing copper lead frame etching during backside preparation on small and non-exposed die paddle package. The drawback of this technique is that the copper leads will be over etched by 65% Acid Nitric Fuming even though the device’s leads are protected by chemical resistance tape. Consequently, the device is not able to proceed to any other further electrical measurements. Therefore, we introduced mechanical preparation as an alternative solution to replace the existing procedure. With the new method, we are able to ensure the copper leads are intact for the electrical measurements to improve the effectiveness and accuracy of physical failure analysis.

Basic Physics in Color-Coded EOS Metallization Failures (Differentiating between EOS and ESD)

1998 ◽  
Author(s):  
Leo G. Henry ◽  
J.H. Mazur
Keyword(s):  
Failure Analysis ◽  
Light Microscope ◽  
Structural Changes ◽  
Surface Oxide ◽  
Aluminum Surface ◽  
Surrounding Area ◽  
Die Surface ◽  
Basic Physics ◽  
Direct Contrast ◽  
Glass Interface

Abstract The task of differentiating precisely between EOS and ESD failures continues to be a challenging one for Failure Analysis Engineers. Electrical OverStress (EOS) failures on the die surface (burnt/fused metallization) of an IC can be characterized mainly by the discoloration at the site of the failures. This is in direct contrast to the lack of discoloration characteristic of ESD failures, which occur almost exclusively below the die surface (oxide and junction failures). To aid in this distinction, this paper attempts to present the underlying physics behind the discoloration produced in the EOS failures. For the EOS failures, the metal fuses due to the longer pulse widths (sec to msec), while for the ESD failures, the silicon melts because of the shorter pulse widths (< < 500 nsec) and higher energy. After EOS, the aluminum surface becomes dark and rough and the oxide in the surrounding area becomes deformed and distorted, resulting in the discoloration observed in the light microscope. This EOS discoloration could be due to one or more of the following: 1) morphological and structural changes at the metal/glass interface and the glass itself; 2) changes in the thickness and scattering behavior of the glass and metal in the failed areas.

Nanoprobing Applications with Capacitance-Voltage and Pulsed Current-Voltage Measurements for Device Failure Analysis

2015 ◽  
Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Pulsed Current ◽  
Electrical Measurements ◽  
Device Failure ◽  
Mos Devices ◽  
Atomic Force ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Rising Time

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.

Fine MCP Decapsulation Technology Development

2006 ◽  
Author(s):  
Jianwei Zhou ◽  
Wei Zheng ◽  
Taekoo Lee
Keyword(s):  
Chemical Etching ◽  
Etch Rate ◽  
Technology Development ◽  
New Technology ◽  
Ammonium Hydroxide ◽  
Mechanical Polishing ◽  
Technology Process ◽  
Tetra Methyl Ammonium Hydroxide ◽  
Die Surface

Abstract Multi-Chip Package (MCP) decapsulation is now becoming a rising problem. Because for traditional decapsulation method, acid can’t dissolve the top silicon die to expose the bottom die surface in MCP. It makes inspecting the bottom die in MCP is difficult. In this paper, a new MCP decapsulation technology combining mechanical polishing with chemical etching is introduced. This new technology can remove the top die quickly without damaging the bottom die using KOH and Tetra-Methyl Ammonium Hydroxide (TMAH). The technology process and relative application are presented. The factors that affect the KOH and TMAH etch rate are studied. The usage difference between the two etchant is discussed.

Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

2002 ◽  
Author(s):  
Hui Pan ◽  
Thomas Gibson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Charge Pump ◽  
Front Side ◽  
Pump Failure ◽  
Electrical Failure ◽  
Optical Proximity Correction ◽  
A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

Interfacial Delamination in Plastic Encapsulated Integrated Circuits (Pics)

1996 ◽  
Vol 445 ◽  
Author(s):  
Nickolaos Strifas ◽  
Aris Christou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Stress Corrosion ◽  
Integrated Circuit ◽  
Point Of View ◽  
Acoustic Microscopy ◽  
Electrical Performance ◽  
Premature Failure ◽  
Interfacial Delamination ◽  
Die Surface

AbstractThe reliability of plastic packaged integrated circuits was assessed from the point of view of interfacial mechanical integrity. It is shown that the effect of structural weaknesses caused by poor bonding, voids, microcracks or delamination may not be evident in the electrical performance characteristics, but may cause premature failure. Acoustic microscopy (C-SAM) was selected for nondestructive failure analysis of the plastic integrated circuit (IC) packages. Integrated circuits in plastic dual in line packages were initially subjected to temperature (25 °C to 85 °C) and humidity cycling (50 to 85 %) where each cycle was of one hour duration and for over 100 cycles and then analyzed. Delamination at the interfaces between the different materials within the package, which is a major cause of moisture ingress and subsequent premature package failure, was measured. The principal areas of delamination were found along the leads extending from the chip to the edge of the molded body and along the die surface itself. Images of the 3-D internal structure were produced that were used to determine the mechanism for a package failure. The evidence of corrosion and stress corrosion cracks in the regions of delamination was identified.

Synthesis of Silicon Nanowire Arrays by Metal-Assisted Chemical Etching in Aqueous NH4HF2 Solution

2012 ◽  
Vol 21 ◽  
pp. 109-115 ◽  
Author(s):  
S. Naama ◽  
T. Hadjersi ◽  
G. Nezzal ◽  
L. Guerbous
Keyword(s):  
Silicon Nanowires ◽  
Chemical Etching ◽  
Silicon Nanowire ◽  
Nanowire Arrays ◽  
Etching Time ◽  
Silicon Nanowire Arrays ◽  
Peak Intensity ◽  
One Step ◽  
Etching Parameters ◽  
P Type

One-step metal-assisted electroless chemical etching of p-type silicon substrate in NH4HF2/AgNO3 solution was investigated. The effect of different etching parameters including etching time, temperature, AgNO3 concentration and NH4HF2 concentration were investigated. The etched layers formed were investigated by scanning electron microscopy (SEM) and Photoluminescence. It was found that the etched layer was formed by well-aligned silicon nanowires. It is noted that their density and length strongly depend on etching parameters. Room temperature photoluminescence (PL) from etched layer was observed. It was observed that PL peak intensity increases significantly with AgNO3 concentration.

Development of moisture-proof thin and large QFP with copper lead frame

2002 ◽  
Author(s):  
T. Mino ◽  
K. Sawada ◽  
A. Kurosu ◽  
M. Otsuka ◽  
N. Kawamura ◽  
...  
Keyword(s):  
Lead Frame ◽  
Copper Lead

Copper lead frame: an ultimate solution to the reliability of BLP package

2000 ◽  
Vol 23 (1) ◽  
pp. 32-38 ◽  
Author(s):  
Kwang-Seong Choi ◽  
Teck-Gyu Kang ◽  
Ik-Seong Park ◽  
Jong-Hyun Lee ◽  
Ki-Bon Cha
Keyword(s):  
Lead Frame ◽  
Copper Lead
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