scholarly journals β-Ga2O3 material properties, growth technologies, and devices: a review

2022 ◽  
Vol 32 (1) ◽  
Author(s):  
Masataka Higashiwaki
Keyword(s):  
Material Properties ◽  
Film Growth ◽  
Field Effect Transistors ◽  
Large Diameter ◽  
Current Status ◽  
Power Switching ◽  
Processing Technologies ◽  
Device Processing ◽  
Bulk Single Crystals ◽  
Device Applications

AbstractRapid progress in β-gallium oxide (β-Ga2O3) material and device technologies has been made in this decade, and its superior material properties based on the very large bandgap of over 4.5 eV have been attracting much attention. β-Ga2O3 appears particularly promising for power switching device applications because of its extremely large breakdown electric field and availability of large-diameter, high-quality wafers manufactured from melt-grown bulk single crystals. In this review, after introducing material properties of β-Ga2O3 that are important for electronic devices, current status of bulk melt growth, epitaxial thin-film growth, and device processing technologies are introduced. Then, state-of-the-art β-Ga2O3 Schottky barrier diodes and field-effect transistors are discussed, mainly focusing on development results of the author’s group.

Low Temperature Device Processing Technology for II-VI Semiconductors

1989 ◽  
Vol 161 ◽  
Author(s):  
D.L. Dreifus ◽  
R.M. Kolbas ◽  
B.P. Sneed ◽  
J.F. Schetzina
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Epitaxial Layers ◽  
Processing Technologies ◽  
Device Processing ◽  
Device Structures ◽  
Lift Off ◽  
Processing Steps

ABSTRACTLow temperature (<60° C) processing technologies that avoid potentially damaging processing steps have been developed for devices fabricated from II-VI semiconductor epitaxial layers grown by photoassisted molecular beam epitaxy (MBE). These low temperature technologies include: 1) photolithography (1 µm geometries), 2) calibrated etchants (rates as low as 30 Å/s), 3) a metallization lift-off process employing a photoresist profiler, 4) an interlevel metal dielectric, and 5) an insulator technology for metal-insulator-semiconductor (MIS) structures. A number of first demonstration devices including field-effect transistors and p-n junctions have been fabricated from II-VI epitaxial layers grown by photoassisted MBE and processed using the technology described here. In this paper, two advanced device structures, processed at <60° C, will be presented: 1) CdTe:As-CdTe:In p-n junction detectors, grown in situ by photoassisted MBE, and 2) HgCdTe-HgTe-CdZnTe quantum-well modulation-doped field-effect transistors (MODFETs).

Growth study of epitaxial FexZn1−xF2 thin films

2001 ◽  
Vol 16 (6) ◽  
pp. 1769-1775 ◽  
Author(s):  
J. McChesney ◽  
M. Hetzer ◽  
H. Shi ◽  
T. Charlton ◽  
D. Lederman
Keyword(s):  
Thin Films ◽  
Film Growth ◽  
Magnetic Phase Diagram ◽  
Epitaxial Thin Films ◽  
X Ray Diffraction ◽  
Growth Study ◽  
Lattice Match ◽  
Different Temperatures ◽  
Bulk Single Crystals ◽  
The Ideal

The FexZn1−xF2 alloy has been shown to be a model system for studying the magnetic phase diagram of dilute magnets. Whereas the growth of bulk single crystals with fixed Zn concentrations is difficult, the thin film growth is comparatively simpler and more flexible. To gain an understanding of the growth of FexZn1−xF2 films, a method was developed to grow smooth films at fixed concentrations. This was done by depositing a MgF2 buffer layer on MgF2(001) substrates and then depositing FeF2 and ZnF2 [001]-orientated epitaxial thin films at different temperatures. Surprisingly, the lattice spacing depends strongly on the growth temperature, for 44-nm-thick FeF2 films and 77-nm-thick ZnF2 films. This indicates a significant amount of stress, despite the close lattice match between the films and the MgF2 substrate. Thick alloy samples (approximately 500 nm thick) were grown by co-evaporation from the FeF2 and ZnF2 sources at the ideal temperature determined from the growth study, and their concentration was accurately determined using x-ray diffraction.

Study of Pullout Performance of Self-Tapping Screws for Human Bone

2011 ◽  
Author(s):  
Zhijun Wu ◽  
Sayed A. Nassar ◽  
Xianjie Yang
Keyword(s):  
Finite Element ◽  
Stress Distribution ◽  
Analytical Model ◽  
Material Properties ◽  
Pedicle Screws ◽  
Pullout Strength ◽  
Bone Material ◽  
Synthetic Bone ◽  
Failure Propagation ◽  
Device Applications

The study investigates the pullout strength of self-tapping pedicle screws using analytical, finite element, and experimental methodologies with focus on medical device applications. The stress distribution and failure propagation around implant threads in the synthetic bone during the pullout process, as well as the pullout strength of pedicle screws, are explored. Based on the FEA results, an analytical model for the pullout strength of the pedicle screw is constructed in terms of the synthetic bone material properties, screw size, and implant depth. The characteristics of pullout behavior of self-tapping pedicle screws are discussed. Both the analytical model and finite element results are validated using experimental techniques.

scholarly journals Effects of Doping Concentration on Device Performance of GaN-based Nano-regime MOSFETs

2017 ◽  
Vol 16 (1) ◽  
pp. 69-74
Author(s):  
Md Iktiham Bin Taher ◽  
Md. Tanvir Hasan
Keyword(s):  
Field Effect ◽  
Doping Concentration ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Gate Length ◽  
Drain Voltage ◽  
Switching Device ◽  
Device Applications

Gallium nitride (GaN) based metal-oxide semiconductor field-effect transistors (MOSFETs) are promising for switching device applications. The doping of n- and p-layers is varied to evaluate the figure of merits of proposed devices with a gate length of 10 nm. Devices are switched from OFF-state (gate voltage, VGS = 0 V) to ON-state (VGS = 1 V) for a fixed drain voltage, VDS = 0.75 V. The device with channel doping of 1×1016 cm-3 and source/drain (S/D) of 1×1020 cm-3 shows good device performance due to better control of gate over channel. The ON-current (ION), OFF-current (IOFF), subthreshold swing (SS), drain induce barrier lowering (DIBL), and delay time are found to be 6.85 mA/μm, 5.15×10-7 A/μm, 87.8 mV/decade, and 100.5 mV/V, 0.035 ps, respectively. These results indicate that GaN-based MOSFETs are very suitable for the logic switching application in nanoscale regime.

Effect of ozone exposure on the electrical characteristics of high-purity, large-diameter semiconducting carbon nanotubes

2014 ◽  
Vol 16 (22) ◽  
pp. 10861-10865 ◽  
Author(s):  
Jia Gao ◽  
Yueh-Lin Loo
Keyword(s):  
Carbon Nanotubes ◽  
High Purity ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Large Diameter ◽  
Ozone Exposure ◽  
Electrical Characteristics

Presorted, semiconducting carbon nanotubes in the channels of field-effect transistors undergo simultaneous p-doping and oxidation during ozone exposure.

Inverter design with positive feedback field-effect transistors

2021 ◽  
Author(s):  
Changhoon Lee ◽  
Changwoo Han ◽  
Changhwan Shin
Keyword(s):  
Positive Feedback ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Feedback Mechanism ◽  
Silicon On Insulator ◽  
Logic Device ◽  
Device Applications ◽  
Positive Feedback Mechanism ◽  
Switching Devices

Abstract As the physical size of semiconductor devices continues to be aggressively scaled down, feedback field-effect transistors (FBFET) with a positive feedback mechanism among a few promising steep switching devices have received attention as next-generation switching devices. Conventional FBFETs have been studied to explore their device performance. However, this has been restricted to the case of single FBFET; basic circuit designs with FBFETs have not been investigated extensively. In this work, we propose an inverter circuit design with silicon-on-insulator (SOI) FBFETs; we verified this inverter design with mixed-mode technology computer-aided design simulation. The basic principles and mechanisms for designing FBFET inverter circuits are explained because their configuration is different from conventional inverters. In addition, the device parameters necessary to optimize circuit construction are introduced for logic device applications.

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