Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly

Abstract Cu pillar micro-bumps with polymer cores have been demonstrated to effectively reduce thermomechanical stress and improve joint reliability. Fabricating polymer cores by a printing approach was proposed to overcome the limitations in conventional fabrication process. Cylindrical polymer cores with diameter of 20 µm and height of 30 µm were successfully printed. Surface metallization was subsequently applied on the printed polymer cores and Cu pillar micro-bumps with printed polymer cores with diameter of 35 µm and height of 35 µm were eventually achieved. To study the reliability performance of the interconnect joints made of Cu pillar micro-bumps with printed polymer cores, flip-chip bonding technology was successfully introduced and the interconnect joints between a designed BT substrate and a silicon chip were formed. The interconnect joints made of conventional Cu pillars with identical dimensions were prepared for comparison. The reliability performance of the joints was investigated under temperature cycling condition and drop condition, respectively. Printed polymer cores increased the characteristic life by 32% in a temperature cycling test (0°C-100°C), while the drop test showed that printed polymer cores increased the characteristic life by 4 times due to the extra compliance provided by the printed polymer cores. It can be concluded that Cu pillar micro-bumps with printed polymer cores can effectively reduce stress and improve joint reliability.

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Cu Pillar flip chip assembly: Chip attach process failure mode study

2014 IEEE 64th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2014.6897448 ◽

2014 ◽

Cited By ~ 2

Author(s):

Shengmin Wen ◽

Bora Baloglu ◽

Guangfeng Li

Keyword(s):

Failure Mode ◽

Flip Chip ◽

Cu Pillar ◽

Process Failure ◽

Flip Chip Assembly ◽

Mode Study

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Chip Package Interaction: Understanding of Contributing Factors in Back End of Line (BEoL) Silicon, Cu Pillar Design and Applied Process Improvements

International Symposium on Microelectronics ◽

10.4071/2380-4505-2018.1.000173 ◽

2018 ◽

Vol 2018 (1) ◽

pp. 000173-000179

Author(s):

Frank Kuechenmeister ◽

Dirk Breuer ◽

Holm Geisler ◽

Bjoern Boehme ◽

Kashi Vishwanath Machani ◽

...

Keyword(s):

Flip Chip ◽

Failure Modes ◽

Process Development ◽

Risk Mitigation ◽

Wafer Level ◽

Contributing Factors ◽

Pillar Design ◽

Process Improvements ◽

Cu Pillar ◽

Volume Production

Abstract This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow. Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.

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