Chip Package Interaction: Understanding of Contributing Factors in Back End of Line (BEoL) Silicon, Cu Pillar Design and Applied Process Improvements

2018 ◽  
Vol 2018 (1) ◽  
pp. 000173-000179
Author(s):  
Frank Kuechenmeister ◽  
Dirk Breuer ◽  
Holm Geisler ◽  
Bjoern Boehme ◽  
Kashi Vishwanath Machani ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Process Development ◽  
Risk Mitigation ◽  
Wafer Level ◽  
Contributing Factors ◽  
Pillar Design ◽  
Process Improvements ◽  
Cu Pillar ◽  
Volume Production

Abstract This paper describes major contributing factors to the CPI risk and reveals the mitigation strategy successfully applied jointly by GLOBALFOUNDRIES as the silicon supplier and Qualcomm Technologies, Inc., as the customer responsible for packaging. This strategy involves thermo-mechanical modelling, data collection on wafer level using shear test to assess the BEoL-stability, Cu Pillar process development and optimization. The qualification of these process changes had been completed and implemented in volume production. The paper also discusses mechanical wafer level and thermo-mechanical package modeling approaches. A model has been applied to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow process. These factors include for instance the Cu Pillar bump geometry and stack up. The results of the modelling work were used to set up experiments to further mitigate CPI related failure modes in BEoL on the package level. GLOBALFOUNDRIES and Qualcomm Technologies, Inc., assessed Cu Pillar design related rules such as Cu Pillar diameter and height as well as the Cu Pillar stack up. Process improvements were carried out to reduce the undercut of the barrier underneath the Cu Pillar. The paper reveals how effectively an optimized Cu Pillar design and improved Cu Pillar processing can contribute to the risk mitigation of CPI failure modes in the BEoL for critical package designs and assembly processes with low margin against BEoL fracture during solder reflow. Furthermore, process improvements applied to enhance the BEoL stack strength were investigated and have been implemented in high-volume production. A strong correlation was established between data collected on wafer level to assess the BEoL strength and data collected on package level.

Effects of Silicon Wafer Bump Pad Structures on Solder and Cu Pillar Flip-Chip Reliability

2016 ◽  
Vol 2016 (1) ◽  
pp. 000100-000105
Author(s):  
Shirley Asoy ◽  
Scott Exon ◽  
Liping Zhu ◽  
Peter Moon ◽  
Michael Carroll ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Flip Chip ◽  
Failure Modes ◽  
Metal Layer ◽  
Production Environment ◽  
Large Area ◽  
Cu Pillar ◽  
Lack Of Information ◽  
Cu Pillar Bump ◽  
Volume Production

Abstract Solder and Cu pillar flip-chip silicon die technologies have been widely used in chip to package mobile module products. During the early design phase, integrated circuit (IC) designers usually apply standard bump design rules, due to lack of information on the reliability of the metal layer stack-up with different bumping processes. However, module reliability data has demonstrated that the stack-up and thickness of the metal layers in a silicon die has a great effect on package stresses, especially for large area Cu pillar flip chip die. In this paper, the effects of bump pad structures on solder and Cu pillar bump reliability have been investigated. A 3D mechanical stress model was developed to compare and optimize various bump structures. A test vehicle with die and module was designed and assembled in a volume production environment. Assembly in-line data was collected and analyzed, and is presented in this paper. Reliability testing and failure analysis were performed to verify the failure modes. Guidelines for designing solder and Cu Pillar Flip-chip bump pad structures have been developed, and are presented in this paper.

DEVELOPMENT OF AN ULTRA THIN DIE-TO-WAFER FLIP CHIP STACKING PROCESS FOR 2.5D INTEGRATION

2013 ◽  
Vol 2013 (1) ◽  
pp. 000516-000522 ◽  
Author(s):  
G. Parès ◽  
A. Attard ◽  
F. Dosseul ◽  
A. N'Hari ◽  
O. Boillon ◽  
...  
Keyword(s):  
Flip Chip ◽  
Transient Liquid Phase ◽  
High Yield ◽  
Integration Scheme ◽  
Wafer Level ◽  
Release Process ◽  
Process Improvements ◽  
Low Profile ◽  
Stress Release Process ◽  
Tin Silver Copper

3D integration relying on novel vertical interconnection technologies opens the gate to powerful microelectronic systems in ultra-thin packages answering the demand of the mobile market. Among these, die-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by, in one hand, the increase of the die surface and the number of I/Os and, on the other hand, the reduction of the vertical dimensions. In our integration scheme we have achieved flip chip stacking (or Face to Face) of 35 μm ultra-thin dies with low stand-off (< 15 μm) copper micro-bumps and tin-silver-copper solders (SAC). Ultra-thin dies are prepared using dicing before grinding (DBG) technique. After DBG, plasma stress release process is applied to the backside of the singulated chips. Copper μbump technology is challenging with this very low profile stacking since the current flip chip process is no longer adapted to this geometry and that the die flatness tolerance become very critical to obtain a high soldering yield. Process improvements have been achieved on the copper pillar fabrication itself with several metallurgy stack configurations as well as new processes using damascene techniques. Furthermore, innovative technologies have been deployed on the pick and place and collective soldering processes. Intermetallic formation during reflow process is achieved through transient liquid phase (TLP) reaction leading to thorough consumption of the tin layer and to the formation of Cu6Sn5 and Cu3Sn compounds. Capillary underfill is finally successfully applied in the narrow die-to-wafer gap by jetting technique. After optimization, electrical tests show a very high yield close to 100% over a representative number of fully populated wafers. Reliability tests have also been carried out at wafer level exhibiting no significant resistance increase or yield loss over 1000 thermal cycles between −40 and +125°C.

Enhanced Cu pillar design to reduce thermomechanical stress induced during flip chip assembly

2018 ◽  
Vol 87 ◽  
pp. 97-105
Author(s):  
Melina Lofrano ◽  
Vladimir Cherman ◽  
Mario Gonzalez ◽  
Eric Beyne
Keyword(s):  
Flip Chip ◽  
Pillar Design ◽  
Thermomechanical Stress ◽  
Cu Pillar ◽  
Flip Chip Assembly

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

A Comparison of Flip Chip Bump Electromigration Reliability for Cu Pillar, High Pb, SnAg, and SnPb Bump Structures

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001443-001464 ◽  
Author(s):  
Ahmer Syed ◽  
Karthikeyan Dhandapani ◽  
Lou Nicholls ◽  
Robert Moody ◽  
C. J. Berry ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Performance Comparison ◽  
Published Data ◽  
Test Vehicle ◽  
Cu Pillar ◽  
Snpb Solder ◽  
Actual Use ◽  
Snag Solder ◽  
Sac Solder

Electromigration failure in flip-chip bumps has emerged as a major reliability concern due to potential elimination of Pb from flip-chip bumps and a continuous drive to increased IO density resulting in a reduction of bump size and pitch. Traditionally, flip-chip interconnects incorporate a high Pb bump soldered with a SnPb eutectic paste to the substrate or another die. However, because of RoHS directives, the industry is responding with Pb free bump development, such as SnAg bump with SAC solder or Cu Pillar with SAC/SnAg solder. Although a number of recent publications deal with electromigration reliability of Pb free and Cu Pillar bumps, a gap exists in terms of their performance comparison with high Pb and SnPb solder on the same bump geometry. The available test data is based on different test vehicles and it becomes difficult to determine the relative performance of these different metallurgies under accelerated test conditions. In addition, not all published data provides the essential parameters of Black's equation to determine the performance and reliability for actual use conditions. This paper attempts to fill this gap by comparing electromigration performance of High Pb, SnPb eutectic, SnAg, and Cu Pillar bumps using the same test vehicle. A special test vehicle was designed with daisy chain structures for electromigration testing and the packages we assembled on test cards. The testing is being done using five (5) stress conditions (combination of current and temperature) to estimate the current density exponent, n, and activation energy, Ea, parameters for Black's equation. The reliability data as well as failure modes for these bump metallurgies will be presented in the paper.

A Generic Strategy to Assess and Mitigate Chip Package Interaction Risk Factors for Semiconductor Devices with Ultra-low k Dielectric Materials in Back End of Line

2017 ◽  
Vol 2017 (1) ◽  
pp. 000163-000171 ◽  
Author(s):  
Frank Kuechenmeister ◽  
Dirk Breuer ◽  
Holm Geisler ◽  
Christian Klewer ◽  
Bjoern Boehme ◽  
...  
Keyword(s):  
Flip Chip ◽  
Dielectric Materials ◽  
Advanced Technology ◽  
Wafer Level ◽  
Contributing Factors ◽  
Related Factors ◽  
Wafer Level Packaging ◽  
Generic Strategy ◽  
Lift Off ◽  
Technology Nodes

Abstract This paper describes a systematic approach to the identification of primary contributing factors to the Chip Package Interaction (CPI) risk and reveals the mitigation strategy successfully applied by GLOBALFOUNDRIES. The strategy includes modeling at bump and package level, gathering experimental data on blanket dielectric back end of line (BEoL) films, collecting data on wafer material with a complete BEoL stack, and finally using readouts on the package level. Advanced measurement methods generate data on the wafer level to achieve fast turn-around times. These methods include: (i) Dual-Cantilever Beam (DCB) test, (ii) Modified Edge Lift-off Test (MELT), (iii) Single Pillar Shear Test (SPST) and (iv) Bump Assisted BEoL Stability Indentation (BABSI) tests. The paper describes the methodology to gather data on the wafer level with a complete BEoL metallization stack that assesses the BEoL integrity. Furthermore, the package level thermomechanical modeling approach is discussed. The model has been used to determine the critical factors on BEoL stress/strain during the flip-chip assembly reflow processes. Silicon design-related factors in the BEoL that contribute to the risk for CPI related failures were investigated and options to reduce the CPI risk are discussed. Finally the paper reveals package level qualification data flip-chip CSP and wafer level packaging Fan-In for advanced technology nodes.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Special Sample Preparation Methodology for Cu Pillar Bump Characterization on Advance Thin Small Leadless Flip Chip with Copper Pillar Bump Interconnect Technology

2018 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Chong Hock Heng
Keyword(s):  
Sample Preparation ◽  
Flip Chip ◽  
High Volume ◽  
Cu Pillar ◽  
Cu Pillar Bump ◽  
High Volume Production ◽  
Special Sample Preparation ◽  
Volume Production ◽  
Wet Etch ◽  
Interconnect Technology

Abstract Today, copper pillar bumping now in high volume production for mobile electronics is also a transformative technology for next generation flip chip [1] interconnects which offers advantages in many designs while meeting current and future requirements. With the continuous shrinking dimensions of semiconductor devices, the package’s design and size are approaching the dimensions of the singulated die. Moreover, failure analysis involving copper pillar packages would be the major challenges faced by analysts as copper pillar devices in nature hides its solder joints beneath its die causing obstruction in quality inspection as well as judging its solder joint strength. Chemical wet etch or deprocessing [2] by using potassium hydroxide (KOH) to remove all silicon die have disadvantages of over etching on silicon substrate and tin (Sn) surrounding the Cu pillar. Therefore, quality of sample preparation is critical and new methodology is needed.

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