Low power-high speed performance of 8T static RAM cell within GaN TFET, FinFET, and GNRFET technologies – A review

2020 ◽  
Vol 163 ◽  
pp. 107665
Author(s):  
Mounica Patnala ◽  
Avinash Yadav ◽  
John Williams ◽  
Anoop Gopinath ◽  
Brian Nutter ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Speed Performance ◽  
Static Ram

A high-speed low-power Hi-CMOS 4K static RAM

1979 ◽  
Vol 26 (6) ◽  
pp. 882-885 ◽  
Author(s):  
O. Minato ◽  
T. Masuhara ◽  
T. Sasaki ◽  
Y. Sakai ◽  
M. Kubo ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Static Ram

scholarly journals IMPLEMENTATION OF HIGH SPEED-LOW POWER TRUNCATION ERROR TOLERANT ADDER

2015 ◽  
pp. 239-244
Author(s):  
SYAM KUMAR NAGENDLA ◽  
K. MIRANJI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Processing System ◽  
Digital Signal ◽  
Signal Processing System ◽  
Speed Performance ◽  
Power Delay Product ◽  
Dsp Systems

Now a Days in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. error tolerant adder(ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved. By operating shifting and addition in parallel, the error tolerant adder tree compensates for the truncation errors. To prove the feasibility of the ETA, normal addition operation present in the DFT or DCT algorithm is replaced by the proposed addition arithmetic and the experimental results are shown. In this paper we propose error tolerant Adder (ETA). In the view of DSP applications the ETA is able to case the strict restriction on accuracy, speed performance and power consumption when compared to the conventional Adders, the proposed one provides 76% improvement in power-delay product such a ETA plays a key role in digital signal processing system that can tolerate certain amount of errors.

Effects of dual-spacer dielectrics on low-power and high-speed performance of sub-10 nm tunneling field-effect transistors

2016 ◽  
Vol 55 (6S1) ◽  
pp. 06GG02 ◽  
Author(s):  
Young Jun Yoon ◽  
Jae Hwa Seo ◽  
Seongjae Cho ◽  
Hyuck-In Kwon ◽  
Jung-Hee Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Tunneling Field Effect Transistors ◽  
Speed Performance

A high-speed, low-power Hi-CMOS 4K static RAM

1978 ◽  
Author(s):  
T. Masuhara ◽  
O. Minato ◽  
T. Sasaki ◽  
Y. Sakai ◽  
M. Kubo ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Static Ram

IVA-4 an ultra-low power, high speed GaAs 256-bit static RAM with depletion mode MESFETs

1983 ◽  
Vol 30 (11) ◽  
pp. 1588-1588 ◽  
Author(s):  
S.J. Lee ◽  
R.P. Vahrenkamp ◽  
G.R. Kaelin ◽  
R. Zucca ◽  
L.D. Hou ◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Ultra Low Power ◽  
Static Ram

scholarly journals A Low Power 6T-Auto Awake Mode-SRAM Design for high speed storage application

2019 ◽  
Vol 8 (9) ◽  
pp. 204-208
Keyword(s):  
Low Power ◽  
High Speed ◽  
Random Access ◽  
Digital World ◽  
Noise Margin ◽  
Sram Cell ◽  
Sram Design ◽  
Static Ram ◽  
Power Application ◽  
Reduced Power Consumption

In the digital world, Static Random Access Memory (SRAM) is one of the efficient core component for electronics design, it consumes huge amount of power and die area. In this research, the SRAM design analysis in terms of read margin, write margin and Static Noise Margin (SNM) for low power application is considered. In SRAM memory, both read and write operation affect by noise margin. So, read and write noise margins are considered as the significant challenges in designing SRAM cell. In this research, robust 6T-SRAM cell is designed to decrease the power utilization. The Auto Awake Mode is developed to control the entire 6T-SRAM cell design. The proposed 6T-SRAM- Auto Awake Mode (6T-SRAM-AAM) was implemented to reduce power utilization of understand and write down operation inside the 20 nm FinFET library. The experimental results showed the proposed 6T-SRAM-AAM design reduced power consumption of read & write operation up to 25% to 33.33% compared to existing Static RAM cells design

scholarly journals Proficient Static RAM design using Sleepy Keeper Leakage Control Transistor & PT-Decoder for handheld application

2019 ◽  
pp. 197-203
Keyword(s):  
Low Power ◽  
High Speed ◽  
Random Access ◽  
Leakage Power ◽  
Access Time ◽  
Sense Amplifier ◽  
Power Simulation ◽  
Sram Cell ◽  
Leakage Control ◽  
Static Ram

Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design. As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application. The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed.

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