A single versatile wideband amplifier from LNA up to MPA

2014 ◽  
Vol 6 (1) ◽  
pp. 23-29
Author(s):  
François-Xavier Estagerie ◽  
Dominique Langrez ◽  
Jean-Luc Muraro ◽  
Jean-Louis Cazaux ◽  
Rémy Leblanc
Keyword(s):  
Noise Figure ◽  
European Space Agency ◽  
Low Noise ◽  
Frequency Range ◽  
Single Chip ◽  
Wideband Amplifier ◽  
Space Agency ◽  
Noise Amplifier ◽  
Initiative Program ◽  
Noise Amplification

This work presents a wideband amplifier, in 12–19 GHz frequency range, with noise figure lower than 1.35 and 26 dB of gain developed in the frame of European Component Initiative program, supported by European Space Agency. By using a flexible biasing, this amplifier allows us to reach a significant linearity, output power at 1 dB compression up to 19 dBm, or to reduce the DC consumption close to 210 mW. This versatility implies that a user has a low-noise amplifier) or medium power amplifier in a single chip. The D01PHS process, from OMMIC foundry, has been chosen in order to realize this MMIC, thanks to linearity capability, and also thanks to a significant potential for low-noise amplification.

scholarly journals GaN-based single-chip frontend for next-generation X-band AESA systems

2018 ◽  
Vol 10 (5-6) ◽  
pp. 660-665 ◽  
Author(s):  
Patrick Schuh ◽  
Hardy Sledzik ◽  
Rolf Reber
Keyword(s):  
Generation X ◽  
Noise Figure ◽  
Power Level ◽  
Input Power ◽  
Low Noise ◽  
Next Generation ◽  
Frequency Range ◽  
Single Chip ◽  
Large Signal ◽  
Integration Density

AbstractA next generation of active electronically scanned array (AESA) antennas will be challenged with the need for lower size, weight, power, and cost. This leads to enhanced demands especially with regard to the integration density of the radio frequency-part inside aT/Rmodule. The semiconductor material GaN has proven its capacity for high-power amplifiers (HPA), robust receive components as well as switch components for separation of transmit and receive mode. This paper will describe the design and measurement results of a GaN-based single-chipT/Rmodule frontend (HPA, low noise anplifier, and single-pole double-throw (SPDT)) using UMS GH25 technology and covering the frequency range from 8 GHz to 12 GHz. The key performance parameters of the frontend are 13 W minimum transmit (TX) output power over the whole frequency range with peak power up to 17 W. The frontend in receive (RX) mode has a noise figure below 3.2 dB over the whole frequency range, and can survive more than 5 W input power. The large signal insertion loss of the used SPDT is below 0.9 dB at 43 dBm input power level.

scholarly journals CMOS Front-End of LNA for GPS and GSM wireless applications

2017 ◽  
Vol 7 (1.5) ◽  
pp. 1
Author(s):  
Mahesh Mudavath ◽  
K. Hari Kishore
Keyword(s):  
Power Dissipation ◽  
Simulation Analysis ◽  
Noise Figure ◽  
Low Cost ◽  
High Sensitivity ◽  
Low Noise ◽  
Frequency Range ◽  
Wireless Applications ◽  
Noise Amplifier ◽  
Intercept Point

This paper describes a layout of a CMOS Low Noise Amplifier for reconfigurable packages which include GPS, GSM Wi-Fi applications. The improvement of a notably linear Radio front-stop, able to function with Galileo and GPS satellite signals suitable for coexisting in a mobile opposed environment for area based offerings, pleasing the fundamental necessities for a mass market product which includes low cost, low footprint, good accuracy, low strength intake and high sensitivity. primarily based on a wideband enter matching, the LNA stages cowl all band of hobby even as reaching a great change-off between excessive gain, low noise parent and coffee electricity intake. The complete simulation analysis of the circuit results in the frequency range of 1.4 GHz to 2 GHz. The noise figure is 1.8 dB at 1.4GHz and rises to 3.4 dB at 2 GHz. The input return and output return losses (S11, S22) of the LNA at a frequency range between 1.4 GHz and 2 GHz are S11= -12 dB, S22 =-44.73 dB at 1.77 GHz and S22 =-26.47 dB at 2 GHz. The overall gain of the LNA (S21) is 13 dB at 1.4025 GHz, 3rd order input intercept point (IIP3) = -3.16 dBm and -1dB compression point is -12.56 dBm. Input Impedance of 50Ω, 3dB Power Bandwidth of 450MHz, and Power Dissipation of 2.7mW at 1.2V power supply.

A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

2013 ◽  
Vol 22 (02) ◽  
pp. 1250088 ◽  
Author(s):  
MERIAM BEN AMOR ◽  
MOURAD LOULOU ◽  
SEBASTIEN QUINTANEL ◽  
DANIEL PASQUET
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Range ◽  
Fully Integrated ◽  
Input Matching ◽  
Noise Amplifier ◽  
Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

scholarly journals Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

2021 ◽  
pp. 85-94
Author(s):  
Dr. Rashmi S B ◽  
Mr. Raghavendra B ◽  
Mr. Sanketh V
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Common Source ◽  
Frequency Range ◽  
Common Gate ◽  
Noise Amplifier

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

scholarly journals Design and Development of Monolithic Microwave Integrated Amplifiers and Coupling Circuits for Telecommunication Systems Applications

2002 ◽  
Vol 25 (1) ◽  
pp. 1-22 ◽  
Author(s):  
R. Makri ◽  
M. Gargalakos ◽  
N. K. Uzunoglu
Keyword(s):  
Fiber Optics ◽  
Noise Figure ◽  
Input Power ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Single Chip ◽  
Telecommunication Systems ◽  
Noise Amplifier ◽  
Shunt Capacitors ◽  
Total Gain

Recent advances in printed circuit and packaging technology of microwave and millimeter wave circuits result to the increasing use of MMICs in telecommunication systems. At Microwave and Fiber Optics Lab of NTUA several designs of various MMICs were conducted using the HP Eesof CAD Tool and FET and HEMT models of F20 and H40 GaAs foundry process of GEC Marconi. The designed MMICs are constructed in Europractice Organization while on-wafer probe measurements are performed in the Lab. In that framework, MMIC technologies are employed in the design of power and low noise amplifiers and couplers to be used for mobile and wireless communications as well as remote sensing and radar applications. A medium power linear FET amplifier has been designed with combining techniques on a single chip. The circuit operates at 14.4–15.2 GHz with an input power of−15dB m, a 36 dB total gain, while the input and output VSWR is less than 1.6. Due to high cost of MMIC fabrication only the first subunit was manufactured and tests verified the simulation results. Additionally, novel techniques have been used for the design of two coupling networks at 10 GHz in order to minimize the area occupied. A meander-kind design as well as shunt capacitors were implemented for a90°quadrature coupler and a Wilkinson one in order to reduce size. Finally, a two stages low noise amplifier was designed with the use of H40 GaAs process in order the differences between the relevant designs to be explored. The key specifications for this MMIC LNA include operation at 10 GHz with a total gain of 17 dB while the noise figure is less than 1.5 dB.

60 GHz-Band Low-Noise Amplifier

2017 ◽  
Vol 26 (05) ◽  
pp. 1750075 ◽  
Author(s):  
Najam Muhammad Amin ◽  
Lianfeng Shen ◽  
Zhi-Gong Wang ◽  
Muhammad Ovais Akhter ◽  
Muhammad Tariq Afridi
Keyword(s):  
Transmission Line ◽  
Quality Factor ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Constant Current ◽  
60 Ghz ◽  
Frequency Range ◽  
Constant Current Density ◽  
Chip Area

This paper presents the design of a 60[Formula: see text]GHz-band LNA intended for the 63.72–65.88[Formula: see text]GHz frequency range (channel-4 of the 60[Formula: see text]GHz band). The LNA is designed in a 65-nm CMOS technology and the design methodology is based on a constant-current-density biasing scheme. Prior to designing the LNA, a detailed investigation into the transistor and passives performances at millimeter-wave (MMW) frequencies is carried out. It is shown that biasing the transistors for an optimum noise figure performance does not degrade their power gain significantly. Furthermore, three potential inductive transmission line candidates, based on coplanar waveguide (CPW) and microstrip line (MSL) structures, have been considered to realize the MMW interconnects. Electromagnetic (EM) simulations have been performed to design and compare the performances of these inductive lines. It is shown that the inductive quality factor of a CPW-based inductive transmission line ([Formula: see text] is more than 3.4 times higher than its MSL counterpart @ 65[Formula: see text]GHz. A CPW structure, with an optimized ground-equalizing metal strip density to achieve the highest inductive quality factor, is therefore a preferred choice for the design of MMW interconnects, compared to an MSL. The LNA achieves a measured forward gain of [Formula: see text][Formula: see text]dB with good input and output impedance matching of better than [Formula: see text][Formula: see text]dB in the desired frequency range. Covering a chip area of 1256[Formula: see text][Formula: see text]m[Formula: see text]m including the pads, the LNA dissipates a power of only 16.2[Formula: see text]mW.

Measurement of a 270 GHz Low Noise Amplifier With 7.5 dB Noise Figure

2007 ◽  
Vol 17 (7) ◽  
pp. 546-548 ◽  
Author(s):  
T. Gaier ◽  
L. Samoska ◽  
A. Fung ◽  
W. R. Deal ◽  
V. Radisic ◽  
...  
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Amplifier

scholarly journals Active Balun with Center-Tapped Inductor and Double-Balanced Gilbert Mixer for GNSS Applications

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1351
Author(s):  
Daniel Pietron ◽  
Tomasz Borejko ◽  
Witold Adam Pleskacz
Keyword(s):  
Phase Shift ◽  
Noise Figure ◽  
Low Noise ◽  
Global Navigation Satellite Systems ◽  
Cmos Process ◽  
Differential Signal ◽  
Satellite Systems ◽  
Active Balun ◽  
Noise Amplifier ◽  
Global Navigation Satellite

A new 1.575 GHz active balun with a classic double-balanced Gilbert mixer for global navigation satellite systems is proposed herein. A simple, low-noise amplifier architecture is used with a center-tapped inductor to generate a differential signal equal in amplitude and shifted in phase by 180°. The main advantage of the proposed circuit is that the phase shift between the outputs is always equal to 180°, with an accuracy of ±5°, and the gain difference between the balun outputs does not change by more than 1.5 dB. This phase shift and gain difference between the outputs are also preserved for all process corners, as well as temperature and voltage supply variations. In the balun design, a band calibration system based on a switchable capacitor bank is proposed. The balun and mixer were designed with a 110 nm CMOS process, consuming only a 2.24 mA current from a 1.5 V supply. The measured noise figure and conversion gain of the balun and mixer were, respectively, NF = 7.7 dB and GC = 25.8 dB in the band of interest.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

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