scholarly journals Design and Development of Monolithic Microwave Integrated Amplifiers and Coupling Circuits for Telecommunication Systems Applications

2002 ◽  
Vol 25 (1) ◽  
pp. 1-22 ◽  
Author(s):  
R. Makri ◽  
M. Gargalakos ◽  
N. K. Uzunoglu
Keyword(s):  
Fiber Optics ◽  
Noise Figure ◽  
Input Power ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Single Chip ◽  
Telecommunication Systems ◽  
Noise Amplifier ◽  
Shunt Capacitors ◽  
Total Gain

Recent advances in printed circuit and packaging technology of microwave and millimeter wave circuits result to the increasing use of MMICs in telecommunication systems. At Microwave and Fiber Optics Lab of NTUA several designs of various MMICs were conducted using the HP Eesof CAD Tool and FET and HEMT models of F20 and H40 GaAs foundry process of GEC Marconi. The designed MMICs are constructed in Europractice Organization while on-wafer probe measurements are performed in the Lab. In that framework, MMIC technologies are employed in the design of power and low noise amplifiers and couplers to be used for mobile and wireless communications as well as remote sensing and radar applications. A medium power linear FET amplifier has been designed with combining techniques on a single chip. The circuit operates at 14.4–15.2 GHz with an input power of−15dB m, a 36 dB total gain, while the input and output VSWR is less than 1.6. Due to high cost of MMIC fabrication only the first subunit was manufactured and tests verified the simulation results. Additionally, novel techniques have been used for the design of two coupling networks at 10 GHz in order to minimize the area occupied. A meander-kind design as well as shunt capacitors were implemented for a90°quadrature coupler and a Wilkinson one in order to reduce size. Finally, a two stages low noise amplifier was designed with the use of H40 GaAs process in order the differences between the relevant designs to be explored. The key specifications for this MMIC LNA include operation at 10 GHz with a total gain of 17 dB while the noise figure is less than 1.5 dB.

scholarly journals GaN-based single-chip frontend for next-generation X-band AESA systems

2018 ◽  
Vol 10 (5-6) ◽  
pp. 660-665 ◽  
Author(s):  
Patrick Schuh ◽  
Hardy Sledzik ◽  
Rolf Reber
Keyword(s):  
Generation X ◽  
Noise Figure ◽  
Power Level ◽  
Input Power ◽  
Low Noise ◽  
Next Generation ◽  
Frequency Range ◽  
Single Chip ◽  
Large Signal ◽  
Integration Density

AbstractA next generation of active electronically scanned array (AESA) antennas will be challenged with the need for lower size, weight, power, and cost. This leads to enhanced demands especially with regard to the integration density of the radio frequency-part inside aT/Rmodule. The semiconductor material GaN has proven its capacity for high-power amplifiers (HPA), robust receive components as well as switch components for separation of transmit and receive mode. This paper will describe the design and measurement results of a GaN-based single-chipT/Rmodule frontend (HPA, low noise anplifier, and single-pole double-throw (SPDT)) using UMS GH25 technology and covering the frequency range from 8 GHz to 12 GHz. The key performance parameters of the frontend are 13 W minimum transmit (TX) output power over the whole frequency range with peak power up to 17 W. The frontend in receive (RX) mode has a noise figure below 3.2 dB over the whole frequency range, and can survive more than 5 W input power. The large signal insertion loss of the used SPDT is below 0.9 dB at 43 dBm input power level.

A single versatile wideband amplifier from LNA up to MPA

2014 ◽  
Vol 6 (1) ◽  
pp. 23-29
Author(s):  
François-Xavier Estagerie ◽  
Dominique Langrez ◽  
Jean-Luc Muraro ◽  
Jean-Louis Cazaux ◽  
Rémy Leblanc
Keyword(s):  
Noise Figure ◽  
European Space Agency ◽  
Low Noise ◽  
Frequency Range ◽  
Single Chip ◽  
Wideband Amplifier ◽  
Space Agency ◽  
Noise Amplifier ◽  
Initiative Program ◽  
Noise Amplification

This work presents a wideband amplifier, in 12–19 GHz frequency range, with noise figure lower than 1.35 and 26 dB of gain developed in the frame of European Component Initiative program, supported by European Space Agency. By using a flexible biasing, this amplifier allows us to reach a significant linearity, output power at 1 dB compression up to 19 dBm, or to reduce the DC consumption close to 210 mW. This versatility implies that a user has a low-noise amplifier) or medium power amplifier in a single chip. The D01PHS process, from OMMIC foundry, has been chosen in order to realize this MMIC, thanks to linearity capability, and also thanks to a significant potential for low-noise amplification.

scholarly journals A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 785
Author(s):  
Juan L. Castagnola ◽  
Fortunato C. Dualibe ◽  
Agustín M. Laprovitta ◽  
Hugo García-Vázquez
Keyword(s):  
Integrated Circuits ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Optimization Approach ◽  
Scattering Parameters ◽  
Rf Integrated Circuits ◽  
Design And Optimization ◽  
Noise Amplifier

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.

A 79GHz Adaptive Gain Low Noise Amplifier for Radar Receivers

2018 ◽  
Vol 7 (2.24) ◽  
pp. 227
Author(s):  
J Manjula ◽  
A Ruhan Bevi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
Input Power ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Common Source ◽  
Adaptive Biasing ◽  
Noise Amplifier

This paper presents an Adaptive Gain 79GHz Low Noise Amplifier (LNA) suitable for Radars applications. The circuit schematic is a two stage LNA consists of Differential cascode configuration followed by a simple common source amplifier with an Adaptive Biasing (ADB) circuit. Adaptive biasing is a three- stage common source amplifier to decrease output voltage as input power increases. The circuit is simulated in 180nm CMOS technology and the simulation results have proved that the circuit operates at the center frequency 79GHz with adaptive biasing for adaptive gain. The gain analysis shows a decrease of 35-30dB with an increase in input power -50 to 0 dB. At 79GHz the circuit has achieved the input reflection coefficient (S11) of -24.7dB, reverse isolation (S12) of -3 dB, forward transmission coefficient (S21) of -2.97dB and output reflection coefficient (S22) of -5.62 dB with the reduced noise figure of 0.9 dB and a power consumption of 236 mW.  

scholarly journals Ultra compact multi-standard low-noise amplifiers in 28 nm CMOS with inductive peaking

2017 ◽  
Vol 10 (1) ◽  
pp. 47-57
Author(s):  
Elena Sobotta ◽  
Guido Belfiore ◽  
Frank Ellinger
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Bandwidth Enhancement ◽  
Dc Power ◽  
Active Inductors ◽  
Inductive Peaking ◽  
Noise Amplifier ◽  
28 Nm

This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process. The transistor parameters were optimized by the gm/ID method taking into account the parasitics and the behavior of highly scaled transistors. To cover the industrial science medical (ISM)-bands around 2.4 and 5.8 GHz, the WLAN band as well as the Ku band a bandwidth enhancement is required. Two versions of LNAs, one with vertical inductors and one with active inductors, are implemented and verified by measurements. The noise figure (NF) exhibits 4.2 dB for the LNA with active inductors and 3.5 dB for the LNA with vertical inductors. The voltage gain reaches 12.8 and 13.4 dB, respectively, with a 3 dB-bandwidth of 20 GHz. Both input referred 1-dB-compression points are higher than −12 dBm making the chips attractive for communication standards with high linearity requirements. The chips consume 53 mW DC power and the LNA with active inductors occupies a core area of only 0.0018 mm2, whereas the version with vertical inductors requires 0.021 mm2.

scholarly journals CMOS low noise amplifiers for 1.575 GHz GPS applications

2009 ◽  
Vol 7 ◽  
pp. 145-150 ◽  
Author(s):  
M. Isikhan ◽  
A. Richter
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Performance Criteria ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Quality Factors ◽  
Voltage Range ◽  
Noise Amplifier ◽  
On Chip

Abstract. This paper presents Low Noise Amplifier (LNA) versions designed for 1.575 GHz L1 Band Global Positioning System (GPS) applications. A 0.35 μm standard CMOS process is used for implementation of these design versions. Different versions are designed to compare the results, analyze some effects and optimize some critical performance criteria. On-chip inductors with different quality factors and a slight topology change are utilized to achieve this variety. It is proven through both on-wafer and on-PCB measurements that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and achieve a gain of 13 dB to 17 dB with a Noise Figure (NF) of 1.5 dB. Input referred 1 dB compression point (ICP) is measured as −5.5 dBm and −10 dBm for different versions.

Measurement of a 270 GHz Low Noise Amplifier With 7.5 dB Noise Figure

2007 ◽  
Vol 17 (7) ◽  
pp. 546-548 ◽  
Author(s):  
T. Gaier ◽  
L. Samoska ◽  
A. Fung ◽  
W. R. Deal ◽  
V. Radisic ◽  
...  
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Amplifier

scholarly journals Active Balun with Center-Tapped Inductor and Double-Balanced Gilbert Mixer for GNSS Applications

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1351
Author(s):  
Daniel Pietron ◽  
Tomasz Borejko ◽  
Witold Adam Pleskacz
Keyword(s):  
Phase Shift ◽  
Noise Figure ◽  
Low Noise ◽  
Global Navigation Satellite Systems ◽  
Cmos Process ◽  
Differential Signal ◽  
Satellite Systems ◽  
Active Balun ◽  
Noise Amplifier ◽  
Global Navigation Satellite

A new 1.575 GHz active balun with a classic double-balanced Gilbert mixer for global navigation satellite systems is proposed herein. A simple, low-noise amplifier architecture is used with a center-tapped inductor to generate a differential signal equal in amplitude and shifted in phase by 180°. The main advantage of the proposed circuit is that the phase shift between the outputs is always equal to 180°, with an accuracy of ±5°, and the gain difference between the balun outputs does not change by more than 1.5 dB. This phase shift and gain difference between the outputs are also preserved for all process corners, as well as temperature and voltage supply variations. In the balun design, a band calibration system based on a switchable capacitor bank is proposed. The balun and mixer were designed with a 110 nm CMOS process, consuming only a 2.24 mA current from a 1.5 V supply. The measured noise figure and conversion gain of the balun and mixer were, respectively, NF = 7.7 dB and GC = 25.8 dB in the band of interest.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

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