scholarly journals Reliability analysis of BiCMOS SiGe:C technology under aggressive conditions for emerging RF and mm-wave applications: proposal of reliability-aware circuit design methodology

2018 ◽  
Vol 10 (5-6) ◽  
pp. 690-699
Author(s):  
Insaf Lahbib ◽  
Sidina Wane ◽  
Aziz Doukkali ◽  
Dominique Lesénéchal ◽  
Thanh Vinh Dinh ◽  
...  

AbstractIn this contribution, the impact of extreme environmental conditions in terms of energy-level radiation of protons on silicon–germanium (SiGe)-integrated circuits is experimentally studied. Canonical representative structures including linear (passive interconnects/antennas) and non-linear (low-noise amplifiers) are used as carriers for assessing the impact of aggressive stress conditions on their performances. Perspectives for holistic modeling and characterization approaches accounting for various interaction mechanisms (substrate resistivity variations, couplings/interferences, drift in DC and radio frequency (RF) characteristics) for active samples are down to allow for optimal solutions in pushing SiGe technologies toward applications with harsh and radiation-intense environments (e.g. space, nuclear, military). Specific design prototypes are built for assessing mission-critical profiles for emerging RF and mm-wave applications.

2020 ◽  
Vol 2020 (1) ◽  
pp. 000125-000130
Author(s):  
Leo Hu ◽  
Sze Pei Lim

Abstract With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.


Author(s):  
Gianluca Cornetta ◽  
David J. Santos ◽  
José Manuel Vázquez

The modern wireless communication industry is demanding transceivers with a high integration level operating in the gigahertz frequency range. This, in turn, has prompted intense research in the area of monolithic passive devices. Modern fabrication processes now provide the capability to integrate onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers, baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and the modeling of integrated capacitors are well understood, the design of an integrated inductor is still a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, making difficult the design of critical parameters such as the self-resonant frequency, the quality factor, and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, integrated inductors still allow for the implementation of integrated circuits with improved performances under low supply voltage. In this chapter, the authors review the technology behind monolithic capacitors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical implementation and modeling.


1996 ◽  
Vol 74 (S1) ◽  
pp. 159-166
Author(s):  
D. C. Ahlgren ◽  
S. J. Jeng ◽  
D. Nguyen-Ngoc ◽  
K. Stein ◽  
D. Sunderland ◽  
...  

This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.


Author(s):  
Arjuna Marzuki

This chapter deals with the concept of first time right IC. A development of subsystems for wireless application is used as test case. The subsystems are Low Noise Amplifier (LNA), Medium Power Amplifier (MPA) and Variable Signal Generator (VSG). Several issues such as suitable multiband design flow and high speed switch must be solved. A new design methodology of integrated circuits for multiband application is presented. The design methodology is modified from a typical Monolithic Microwave Integrated Circuit (MMIC) flow. Core based design, parasitic aware approach and power constrained optimization are introduced into the new design flow. The same core circuit topology is used as main block to design 2.4 GHz and 3.5 GHz LNA and MPA. A power constrained optimization is applied to a test case amplifier i.e. broadband amplifier to get the optimized RF performance. The optimization is simulation-based technique. A 0.15 µm 85 GHz PHEMT is used in designing the LNA, MPA and broadband amplifier. This chapter also introduces the inventions of Voltage Controlled Oscillator (VCO), Mixer, Low Noise Amplifiers (LNA), Power Amplifiers (PA) and Transmit-Receive Switch (T/R). These circuits are crucial components for RF and Microwave front-end integrated circuits. The elements of inventions of circuits are clearly explained. The inventions reflect the requirement or the need of solving current problem using available technology.


2020 ◽  
Vol 11 ◽  
pp. 1316-1320
Author(s):  
Ilya L Novikov ◽  
Boris I Ivanov ◽  
Dmitri V Ponomarev ◽  
Aleksey G Vostretsov

We designed, implemented, and characterized differential amplifiers for cryogenic temperatures based on Si bipolar junction transistor technology. The amplifiers show high gain values of more than 60 dB at 300, 77, and 48 K. The minimum voltage noise spectral density was achieved at 77 K and corresponded to 0.33 nV/Hz0.5 with a flicker noise of 20 Hz. The maximum voltage gain was 70 dB at 77 K for a frequency range from DC to 17 kHz. We experimentally show that the parallel differential circuit design allows for a reduction of the voltage noise from 0.55 to 0.33 nV/Hz0.5 at 77 K.


2008 ◽  
Vol 2008 ◽  
pp. 1-8 ◽  
Author(s):  
Goran Stojanović ◽  
Milan Radovanović ◽  
Vasa Radonić

Silicon-based radio-frequency integrated circuits are becoming more and more competitive in wide-band frequency range. An essential component of these ICs is on-chip (integrated) transformer. It is widely used in mobile communications, microwave integrated circuits, low-noise amplifiers, active mixers, and baluns. This paper deals with the design, simulation, and analysis of novel fractal configurations of the primary and secondary coils of the integrated transformers. Integrated stacked transformers, which use fractal curves (Hilbert, Peano, and von Koch) to form the primary and secondary windings, are presented. In this way, the occupied area on the chip is lower and a number of lithographic processes are decreased. The performances of the proposed integrated transformers are investigated with electromagnetic simulations up to 20 GHz. The influence of the order of fractal curves and the width of conductive lines on the inductance and quality factor is also described.


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