scholarly journals Photoluminescence enhancement by deterministically site-controlled, vertically stacked SiGe quantum dots

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Jeffrey Schuster ◽  
Johannes Aberl ◽  
Lada Vukušić ◽  
Lukas Spindlberger ◽  
Heiko Groiss ◽  
...  
Keyword(s):  
Light Emission ◽  
Thermal Quenching ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Strain Engineering ◽  
Nucleation Site ◽  
Oxide Semiconductor ◽  
Light Sources ◽  
Indirect Band Gap ◽  
Sige Quantum Dot

AbstractThe Si/SiGe heterosystem would be ideally suited for the realization of complementary metal-oxide-semiconductor (CMOS)-compatible integrated light sources, but the indirect band gap, exacerbated by a type-II band offset, makes it challenging to achieve efficient light emission. We address this problem by strain engineering in ordered arrays of vertically close-stacked SiGe quantum dot (QD) pairs. The strain induced by the respective lower QD creates a preferential nucleation site for the upper one and strains the upper QD as well as the Si cap above it. Electrons are confined in the strain pockets in the Si cap, which leads to an enhanced wave function overlap with the heavy holes near the upper QD’s apex. With a thickness of the Si spacer between the stacked QDs below 5 nm, we separated the functions of the two QDs: The role of the lower one is that of a pure stressor, whereas only the upper QD facilitates radiative recombination of QD-bound excitons. We report on the design and strain engineering of the QD pairs via strain-dependent Schrödinger-Poisson simulations, their implementation by molecular beam epitaxy, and a comprehensive study of their structural and optical properties in comparison with those of single-layer SiGe QD arrays. We find that the double QD arrangement shifts the thermal quenching of the photoluminescence signal at higher temperatures. Moreover, detrimental light emission from the QD-related wetting layers is suppressed in the double-QD configuration.

scholarly journals All-optical modulation based on MoS2-Plasmonic nanoslit hybrid structures

Nanophotonics ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Feiying Sun ◽  
Changbin Nie ◽  
Xingzhan Wei ◽  
Hu Mao ◽  
Yupeng Zhang ◽  
...  
Keyword(s):  
High Efficiency ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Optical Modulator ◽  
Small Scale ◽  
Light Modulation ◽  
Optical Modulators ◽  
Signal Light ◽  
All Optical

Abstract Two-dimensional (2D) materials with excellent optical properties and complementary metal-oxide-semiconductor (CMOS) compatibility have promising application prospects for developing highly efficient, small-scale all-optical modulators. However, due to the weak nonlinear light-material interaction, high power density and large contact area are usually required, resulting in low light modulation efficiency. In addition, the use of such large-band-gap materials limits the modulation wavelength. In this study, we propose an all-optical modulator integrated Si waveguide and single-layer MoS2 with a plasmonic nanoslit, wherein modulation and signal light beams are converted into plasmon through nanoslit confinement and together are strongly coupled to 2D MoS2. This enables MoS2 to absorb signal light with photon energies less than the bandgap, thereby achieving high-efficiency amplitude modulation at 1550 nm. As a result, the modulation efficiency of the device is up to 0.41 dB μm−1, and the effective size is only 9.7 µm. Compared with other 2D material-based all-optical modulators, this fabricated device exhibits excellent light modulation efficiency with a micron-level size, which is potential in small-scale optical modulators and chip-integration applications. Moreover, the MoS2-plasmonic nanoslit modulator also provides an opportunity for TMDs in the application of infrared optoelectronics.

A new approach to bypass wire crossing problem in QCA nano technology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ali Majeed ◽  
Esam Alkaldy
Keyword(s):  
Power Dissipation ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Nano Technology ◽  
New Approach ◽  
Content Type ◽  
Wire Crossing

Purpose This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them. Design/methodology/approach Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder. Findings A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit. Originality/value In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.

Analog Complementary Metal–Oxide–Semiconductor Integrate-and-Fire Neuron Circuit for Overflow Retaining in Hardware Spiking Neural Networks

2020 ◽  
Vol 20 (5) ◽  
pp. 3117-3122
Author(s):  
Sungmin Hwang ◽  
Jeong-Jun Lee ◽  
Min-Woo Kwon ◽  
Myung-Hyun Baek ◽  
Taejin Jang ◽  
...  
Keyword(s):  
Neural Network ◽  
High Performance ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Basic Operation ◽  
Neuron Circuit ◽  
Integrate And Fire ◽  
Analog Cmos ◽  
High Level

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

scholarly journals A highly stable, nanotube-enhanced, CMOS-MEMS thermal emitter for mid-IR gas sensing

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Daniel Popa ◽  
Richard Hopper ◽  
Syed Zeeshan Ali ◽  
Matthew Thomas Cole ◽  
Ye Fan ◽  
...  
Keyword(s):  
Gas Sensing ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Light Sources ◽  
Mir Spectroscopy ◽  
Sensing Applications ◽  
Cmos Mems ◽  
Extended Operation ◽  
On Chip

AbstractThe gas sensor market is growing fast, driven by many socioeconomic and industrial factors. Mid-infrared (MIR) gas sensors offer excellent performance for an increasing number of sensing applications in healthcare, smart homes, and the automotive sector. Having access to low-cost, miniaturized, energy efficient light sources is of critical importance for the monolithic integration of MIR sensors. Here, we present an on-chip broadband thermal MIR source fabricated by combining a complementary metal oxide semiconductor (CMOS) micro-hotplate with a dielectric-encapsulated carbon nanotube (CNT) blackbody layer. The micro-hotplate was used during fabrication as a micro-reactor to facilitate high temperature (>700 $$^{\circ }$$ ∘ C) growth of the CNT layer and also for post-growth thermal annealing. We demonstrate, for the first time, stable extended operation in air of devices with a dielectric-encapsulated CNT layer at heater temperatures above 600 $$^{\circ }$$ ∘ C. The demonstrated devices exhibit almost unitary emissivity across the entire MIR spectrum, offering an ideal solution for low-cost, highly-integrated MIR spectroscopy for the Internet of Things.

scholarly journals A highly stable, nanotube-enhanced, CMOS-MEMS thermal emitter for mid-IR gas sensing

2021 ◽  
Author(s):  
Daniel Popa ◽  
Richard Hopper ◽  
Syed Zeeshan Ali ◽  
Matthew Cole ◽  
Ye Fan ◽  
...  
Keyword(s):  
Gas Sensing ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Light Sources ◽  
Mir Spectroscopy ◽  
Sensing Applications ◽  
Cmos Mems ◽  
Extended Operation ◽  
On Chip

Abstract The gas sensor market is growing fast, driven by many socioeconomic and industrial factors. Mid-infrared (MIR) gas sensors offer excellent performance for an increasing number of sensing applications in healthcare, smart homes, and the automotive sector. Having access to low-cost, miniaturized, energy efficient light sources is of critical importance for the monolithic integration of MIR sensors. Here, we present an on-chip broadband thermal MIR source fabricated by combining a complementary metal oxide semiconductor (CMOS) micro-hotplate with a dielectric-encapsulated carbon nanotube (CNT) blackbody layer. The micro-hotplate was used during fabrication as a micro-reactor to facilitate high temperature (>700 • C) growth of the CNT layer and also for post-growth thermal annealing. We demonstrate, for the first time, stable extended operation in air of devices with a dielectric-encapsulated CNT layer at heater temperatures above 600 • C. The demonstrated devices exhibit almost unitary emissivity across the entire MIR spectrum, offering an ideal solution for low-cost, highly-integrated MIR spectroscopy for the Internet of Sensors.

Real-space strain mapping of SOI features using microbeam X-ray diffraction

2008 ◽  
Vol 23 (2) ◽  
pp. 106-108
Author(s):  
Conal E. Murray ◽  
S. M. Polvino ◽  
I. C. Noyan ◽  
B. Lai ◽  
Z. Cai
Keyword(s):  
Semiconductor Device ◽  
Complementary Metal Oxide Semiconductor ◽  
Strain Engineering ◽  
Real Space ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Strain Mapping ◽  
Strained Si ◽  
X Ray ◽  
Out Of Plane

Synchrotron-based X-ray microbeam measurements were performed on silicon-on-insulator (SOI) features strained by adjacent shallow-trench isolation (STI). Strain engineering in microelectronic technology represents an important aspect of the enhancement in complementary metal-oxide semiconductor device performance. Because of the complexity of the composite geometry associated with microelectronic circuitry, characterization of the strained Si devices at a submicron resolution is necessary to verify the expected strain distributions. The interaction region of the SOI strain extended the SOI film thickness from the STI edge at least 25 times. Regions of 65-nm-thick SOI less than 3 μm wide exhibited an overlap in the strain fields because of the surrounding STI. Microbeam mapping of arrays containing submicron SOI features and embedded STI structures revealed the largest out-of-plane strains because of the close proximity of superimposed strain distributions induced by the STI.

Recent Progress in the Understanding of Si-Nanostructures Formation in a-SiNx:H Thin Film for Si-Based Optoelectronic Devices

2011 ◽  
Vol 171 ◽  
pp. 1-17 ◽  
Author(s):  
Sarab Preet Singh ◽  
Pankaj Srivastava
Keyword(s):  
Silicon Nitride ◽  
Complementary Metal Oxide Semiconductor ◽  
Cost Effective ◽  
Heavy Ion ◽  
Oxide Semiconductor ◽  
Light Sources ◽  
Present Contribution ◽  
Dielectric Matrix ◽  
Si Nanostructures ◽  
Shi Irradiation

There has been a rapidly increasing interest in the synthesis and characterization of Si- nanostructures embedded in a dielectric matrix, as it can lead to energy-efficient and cost-effective Complementary Metal-Oxide-Semiconductor (CMOS)-compatible Si-based light sources for optoelectronic integration. In the present contribution, first an overview of the SiOx as a dielectric matrix and its limitations are discussed. We then review the literature on hydrogenated amorphous silicon nitride (a-SiNx:H) as a dielectric matrix for Si-nanostructures, which have been carried out using silane (SiH4) and ammonia (NH3) as the reactant gases. Our studies demonstrate that the least amount of hydrogen in the as-deposited (ASD) a-SiNx:H films not only allows in-situ formation of Si-nanostructures but also stabilizes silicon nitride (Si3N4) phase. The recent advances made in controlling the shape and size of Si-nanostructures embedded in a-SiNx:H matrix by swift heavy ion (SHI) irradiation are briefly discussed.

scholarly journals State of the Art and Future Perspectives in Advanced CMOS Technology

Nanomaterials ◽  
2020 ◽  
Vol 10 (8) ◽  
pp. 1555 ◽  
Author(s):  
Henry H. Radamson ◽  
Huilong Zhu ◽  
Zhenhua Wu ◽  
Xiaobin He ◽  
Hongxiao Lin ◽  
...  
Keyword(s):  
Semiconductor Industry ◽  
3D Structure ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Strain Engineering ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Technology Roadmap ◽  
Innovative Methods ◽  
Device Processing

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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