scholarly journals The advancement of cluster based FPGA place & route technic

2020 ◽  
Vol 309 ◽  
pp. 01014
Author(s):  
Zhimei Zhou ◽  
Yong Wan ◽  
Yin Liu ◽  
Xiaoyan Guo ◽  
Qilin Yin ◽  
...  
Keyword(s):  
Information Technology ◽  
High Speed ◽  
High Performance ◽  
Design Method ◽  
Digital Signal ◽  
Programmable Logic ◽  
Logic Block ◽  
Chip Technology ◽  
Routing Technology ◽  
Logic Unit

As one of the core components of electronic hardware systems, Field Programmable Logic Array (FPGA) device design technology continues to advance under the guidance of electronic information technology policies, and has made information technology applications. huge contribution. However, with the advancement of chip technology and the continuous upgrading of information technology, the functions that FPGAs need to perform are more and more complicated. How to efficiently perform layout design and make full use of chip resources has become an important technology to be solved and optimized in FPGA design. The FPGA itself is not limited to a specific function. It contains internal functions such as memory, protocol module, clock module, high-speed interface module and digital signal processing. It can be programmed through logic modules such as programmable logic unit modules and interconnects. Blank FPGA devices are designed to be high performance system applications with complex functions. The layout and routing technology based on cluster logic unit blocks can combine the above resources to give full play to its performance advantages, and its importance is self-evident. Based on the traditional FPGA implementation, this paper analyzes several advantages based on cluster logic block layout and routing technology, and generalizes the design method and flow based on cluster logic block layout and routing technology.

scholarly journals A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

2021 ◽  
Vol 11 (16) ◽  
pp. 7554
Author(s):  
Isiaka Alimi ◽  
Romil Patel ◽  
Nuno Silva ◽  
Chuanbowen Sun ◽  
Honglin Ji ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Dynamic Environment ◽  
Digital Signal ◽  
Research Directions ◽  
Recent Advances ◽  
Heterogeneous Nature ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

scholarly journals Development of a High-Speed Digitizer to Time Resolve Nanosecond Fluorescence Pulses

2012 ◽  
Vol 10 (2) ◽  
Author(s):  
E. Moreno-García ◽  
R. Galicia-Mejía ◽  
D. Jiménez-Olarte ◽  
J. M. de la Rosa Vázquez ◽  
S. Stolik-Isakina
Keyword(s):  
Time Domain ◽  
Digital Signal Processor ◽  
High Speed ◽  
High Performance ◽  
Input Pulse ◽  
Control Program ◽  
Sampling Technique ◽  
Digital Signal ◽  
Time Resolved ◽  
The Time Domain

The development of a high-speed digitizer system to measure time-domain voltage pulses in nanoseconds range is presented in this work. The digitizer design includes a high performance digital signal processor, a high-bandwidth analog-to-digital converter of flash-type, a set of delay lines, and a computer to achieve the time-domain measurements. A program running on the processor applies a time-equivalent sampling technique to acquire the input pulse. The processor communicates with the computer via a serial port RS-232 to receive commands and to transmit data. A control program written in LabVIEW 7.1 starts an acquisition routine in the processor. The program reads data from processor point by point in each occurrence of the signal, and plots each point to recover the time-resolved input pulse after n occurrences. The developed prototype is applied to measure fluorescence pulses from a homemade spectrometer. For this application, the LabVIEW program was improved to control the spectrometer, and to register and plot time-resolved fluorescence pulses produced by a substance. The developed digitizer has 750 MHz of analog input bandwidth, and it is able to resolve 2 ns rise-time pulses with 150 ps of resolution and a temporal error of 2.6 percent.

scholarly journals FFT using Power Efficient Vedic Multiplier

2019 ◽  
Vol 8 (10) ◽  
pp. 603-608
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Power Efficient ◽  
Large Numbers ◽  
Vedic Multiplier ◽  
The Right ◽  
Dsp Systems ◽  
Minimal Area

Modern communication systems rely on Digital Signal Processing (DSP) more than ever before. Improving the speed of FFT computation using high speed multipliers will help to enhance the performance of DSP systems. In this paper a DIT FFT architecture using high performance Modified Vedic multipliers is proposed. Vedic Multipliers offer a more efficient way to perform multiplication on large numbers occupying less area and consuming low power and delay The adders used in the Vedic multipliers are Brent Kung based and multiplexer based adders. The right utilization of these adders at different word lengths helps to achieve an architecture with minimal area and power. Comparative analysis of modified 24×24 Vedic Multiplier with existing Vedic Multiplier shows the improvement in performance with respect to power and area. Proposed FFT design is compared with existing designs for dynamic power consumption and an improvement of 46.93% compared to Tsai’s FFT Design and 59.37% compared to Coelho’s FFT Design is achieved. The entire architecture is implemented on Virtex 7 FPGA and simulated using Xilinx Vivado 2017.4.

Low-power consumption seamless wireless and wired links using transparent waveform transfer

2014 ◽  
Vol 3 (5-6) ◽  
Author(s):  
Tetsuya Kawanishi
Keyword(s):  
Power Consumption ◽  
Optical Fiber ◽  
Low Power ◽  
Millimeter Wave ◽  
Optical Fibers ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Low Power Consumption ◽  
Wireless Links

AbstractThis paper describes wired and wireless seamless networks consisting of radiowave and optical fiber links. Digital coherent technology developed for high-speed optical fiber transmission can mitigate signal deformation in radiowave links in the air as well as in optical fibers. Radio-over-fiber (RoF) technique, which transmits radio waveforms on intensity envelops of optical signals, can provide direct waveform transfer between optical and radio signals by using optical-to-electric or electric-to-optical conversion devices. Combination of RoF in millimeter-wave bands and digital coherent with high-performance digital signal processing (DSP) can provide wired and wireless seamless links where bit rate of wireless links would be close to 100 Gb/s. Millimeter-wave transmission distance would be shorter than a few kilometers due to large atmospheric attenuation, so that many moderate distance wireless links, which are seamlessly connected to optical fiber networks should be required to provide high-speed mobile-capable networks. In such systems, reduction of power consumption at media converters connecting wired and wireless links would be very important to pursue both low-power consumption and large capacity.

Design of Universal Signal Processing Machine Based on Multiple DSP

2013 ◽  
Vol 321-324 ◽  
pp. 1241-1244
Author(s):  
Yang Jian ◽  
Yu Hao Liu ◽  
Xi Jing Zhao ◽  
Hao Ming Chen
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Multiple Channel ◽  
Processing Machine ◽  
Large Memory ◽  
High Speed Data ◽  
Board Level

With the development and application of technique on high speed digital signal processing, wide bandwidth processing, high-speed data exchanging and flexible interlink structure have been the developing trend of modern high performance signal processing machine. In this paper, one universal signal processing machine is designed based on six pieces of ADSP-TS201 TigerSHARC processors, which owns good characteristics such as: large memory, excellent processing and data-exchanging performance, reconstitution, good expansibility. This signal processing machine adopts 64Bit, 66MHz CPCI bus standard and supports the function of extending processing performance by interlinking multiple boards. The high-speed data-exchanging is realized with multiple channel optical fiber. Furthermore, it owns board-level BIT function.

scholarly journals Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy

2016 ◽  
Vol 05 (04) ◽  
pp. 1602002 ◽  
Author(s):  
D. C. Price ◽  
J. Kocz ◽  
M. Bailes ◽  
L. J. Greenhill
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Radio Astronomy ◽  
Graphics Processing Units ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
General Purpose ◽  
Special Issue ◽  
Dsp Systems

Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

scholarly journals Ultra high speed full adder for biomedical applications

2021 ◽  
Vol 10 (1) ◽  
pp. 25
Author(s):  
Basavoju Harish ◽  
M. S. S. Rukmini
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Medical Engineering ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Devices ◽  
Ripple Carry Adder ◽  
Power Delay Product

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

scholarly journals Design of a Fault Tolerant Razor Flip Flop Sklansky Adder for Delay Reduction in FIR Filter

2019 ◽  
Vol 8 (9) ◽  
pp. 2647-2651
Keyword(s):  
Fault Tolerance ◽  
High Performance ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Fir Filter ◽  
Delay Reduction ◽  
Flip Flop ◽  
Multiple Faults ◽  
Fault Tolerant System ◽  
Logic Unit

Basically, to reduce the failure rate in the system, we need to introduce the fault tolerant system. Because of multiple faults occurred in the system, the system will increase the area. To employ the adder architecture, different algorithms are used in digital signal processing. By introducing the fault tolerant system, the reliability of the proposed system will increase. So in this paper we introduced the design of fault tolerant razor flip flop using SKLANSKY adder for delay reduction in FIR filter. The razor flip flop will increase the energy efficiency of proposed system. This flip flop will store the information by latching the circuit. The SKLANSKY adder is the part of arithmetic logic unit. In proposed system, all bits are summed and followed to the fault tolerance system,. This fault tolerance system will detect the error and give efficient output. Hence compared to existed system, the proposed system gives high performance and accuracy in terms of delay.

scholarly journals An Optimized CB-UT Multiplier for Efficient Design of the AM Operator

2020 ◽  
Author(s):  
Hari Krishna Modalavalasa
Keyword(s):  
Signal Processing ◽  
Performance Optimization ◽  
High Speed ◽  
High Performance ◽  
New Technology ◽  
Digital Signal ◽  
Propagation Delay ◽  
Efficient Design ◽  
Silicon Area ◽  
Low Area

The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever going demand for the high speed processing and low area design. In today's technology, Add-Multiply (AM) operator or Multiply Accumulator (MAC) units are generally employed in all high performance digital signal processors (DSP) and controllers. The performance of AM operator mainly depends on the speed of multiplier. A lot of research has been contributed in this area and the conventional multipliers were modified to provide good speed performance but needs to be improved further along with area optimization. Urdhwa-Tiryakbhyam Multiplier (UTM) architecture is adopted from ancient Indian mathematics "Vedas’ and can generate the partial products and sums in one step, which reduces the carry propagation from LSB to MSB. UTM can be used to implement high performance AM operators but results in larger silicon areas. This increased area can be minimized by using the modified compressor based design of UTM. In this work, the carrylook-ahead (CLA) adder is adopted instead of parallel adders for high speed of accumulation. So, the Compressor-Based-Urdhwa-Tiryakbhyam (CB-UT) multiplier with CLA results in both area and performance optimization of Add-Multiply operator. The functionality of this architecture is evaluated by comparing with the Modified Booth (MB) multiplier based AM operator in terms of performance parameters like propagation delay, power consumption and silicon-area. The design is implemented and verified using Xilinx Spartan-3E FPGA and ISE Simulator.

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