scholarly journals Spin wave propagation in uniform waveguide: effects, modulation and its application

2022 ◽  
Author(s):  
Lei Zheng ◽  
Lichuan Jin ◽  
Tianlong Wen ◽  
Yulong Liao ◽  
Xiaoli Tang ◽  
...  
Keyword(s):  
Wave Propagation ◽  
Information Transmission ◽  
Spin Wave ◽  
Spin Waves ◽  
Complementary Metal Oxide Semiconductor ◽  
Wide Band ◽  
Oxide Semiconductor ◽  
Research Progress ◽  
Freedom Of Information ◽  
Band Frequency

Abstract With the advent of the post-Moore era, researches on beyond-Complementary Metal Oxide Semiconductor (CMOS) approaches have been attracted more and more attention. Magnonics, or spin wave is one of the most promising technology beyond CMOS, which magnons-quanta for spin waves-process the information analogous to electronic charges in electronics. Information transmission by spin waves, which uses the frequency, amplitude and (or) phase to encode information, has a great many of advantages such as extremely low energy loss and wide-band frequency. Moreover, using the nonlinear characteristics of spin waves for information transmission can increase the extra degree of freedom of information. This review provides a tutorial overview over the effects of spin wave propagation and recent research progress in uniform spin wave waveguide. The propagation characteristics of spin waves in uniform waveguides and some special propagation phenomena such as spin wave beam splitting and self-focusing are described by combining experimental phenomena and theoretical formulas. Furthermore, we summarize methods for modulating propagation of spin wave in uniform waveguide, and comment on the advantages and limitations of these methods. The review may promote the development of information transmission technology based on spin waves.

scholarly journals A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 375
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Successive Approximation ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Wide Band ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Adaptive Power

A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.

scholarly journals Interfacial Dzialoshinskii–Moriya interaction induced nonreciprocity of spin waves in magnonic waveguides

RSC Advances ◽  
2014 ◽  
Vol 4 (87) ◽  
pp. 46454-46459 ◽  
Author(s):  
Fusheng Ma ◽  
Yan Zhou
Keyword(s):  
Wave Propagation ◽  
Spin Wave ◽  
Spin Waves ◽  
Moriya Interaction

Nonreciprocal spin wave propagation in magnonic waveguides with the presence of interfacial Dzialoshinskii–Moriya interaction: different frequencies, amplitudes, and mode profiles.

A Technique to Determine the Designable Inductance Value(s) in Wide-Band CMOS-Amplifier System Employing Shunt-Peaking

2015 ◽  
Vol 24 (08) ◽  
pp. 1550119
Author(s):  
R. Raut ◽  
G. Gibson
Keyword(s):  
Transfer Function ◽  
Design Procedure ◽  
Complementary Metal Oxide Semiconductor ◽  
Wide Band ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Bandwidth Extension ◽  
Constant Frequency ◽  
Common Gate ◽  
Cmos Amplifier

This paper presents a technique towards obtaining an estimate of the value of inductor(s) to expand the bandwidth of operation in a complementary metal-oxide semiconductor (CMOS) amplifier system which exploits shunt peaking principle. The basic principle is placement of the zeros of the transfer function in an interleaved manner relative to the uncompensated RC time-constant frequency (TCF) and the band-edge frequency (BEF) (i.e., product of the poles) of the transfer function. Application of the analytical results has been demonstrated for (i) a common-gate (CG) amplifier stage in a 0.18-μm CMOS process and (ii) an inter-stage inductor coupling network which serves as an interface between two amplifier stages. MATLAB simulation has been used to obtain the range of design inductance values. The TSMC 180-nm CMOS process has been used in Cadence CAD environment to validate the theoretical predictions. The inductors laid out have been modeled using the ASITIC program to obtain more realistic results. The proposed technique provides a bandwidth extension of the CMOS common-gate amplifier from 6.68 GHz to 10.4 GHz with 1 dB peaking using only a 1.85-nH inductor. For the inter-stage coupling network, the suggested design procedure leads to a bandwidth extension ratio (BWER) exceeding three, with less than 3-dB ripple.

Spin wave propagation and nonreciprocity in metallic magnonic quasi-crystals

2021 ◽  
Author(s):  
Takashi Manago ◽  
Kanta Fujii ◽  
Kenji Kasahara ◽  
Kazuyuki Nakayama
Keyword(s):  
Wave Propagation ◽  
Band Gap ◽  
Spin Wave ◽  
Spin Waves ◽  
Fibonacci Sequence ◽  
Propagation Direction ◽  
Band Gaps ◽  
Sequence Length ◽  
Micromagnetic Simulations ◽  
Quasi Crystals

Abstract The characteristics of spin waves propagating in Fibonacci magnonic quasi-crystals (MQCs) were investigated in micromagnetic simulations. The spin waves feel 1/3rd of the characteristic Fibonacci sequence length as a period, and mini band gaps reflected by MQCs are formed. The effect of the MQC on the spin wave’s propagation becomes prominent above the first band gap frequency. The properties of spin waves in MQCs generally depend on the propagation direction, because spin waves feel different structures depending on the direction. Therefore, the nonreciprocity (NR) characteristics becomes complex. The NR characteristics change at every band gap frequency and hence across the frequency regions defined by them. In particular, some frequency regions have almost no NR, while others have enhanced NR and some have even negative NR. These characteristics provide a new way to control NR.

DESIGN OF SPIN WAVE FUNCTIONS-BASED LOGIC CIRCUITS

SPIN ◽  
2012 ◽  
Vol 02 (03) ◽  
pp. 1240006 ◽  
Author(s):  
PRASAD SHABADI ◽  
SANKARA NARAYANAN RAJAPANDIAN ◽  
SANTOSH KHASANVIS ◽  
CSABA ANDRAS MORITZ
Keyword(s):  
Metal Oxide ◽  
Spin Wave ◽  
Complementary Metal Oxide Semiconductor ◽  
Building Blocks ◽  
Metal Oxide Semiconductor ◽  
Wave Functions ◽  
Oxide Semiconductor ◽  
State Variables ◽  
Information Encoding ◽  
Phase Amplitude

Over the past few years, several novel nanoscale computing concepts have been proposed as potential post-complementary metal oxide semiconductor (CMOS) computing fabrics. In these, key focus is on inventing a faster and lower power alternative to conventional metal oxide semiconductor field effect transators. Instead, we propose a fundamental shift in mindset towards more functional building blocks, replacing simple switches with more sophisticated information encoding and computing based on alternate state variables to achieve a significantly more efficient and compact logic. Specifically, we propose wave computation enabled by magnetic spin wave interactions called as spin wave functions (SPWFs). In SPWFs, computation is based on wave interference and information can be encoded in a wave's phase, amplitude and frequency. In this paper, we provide an update on key fabric concepts and design aspects. Our analysis shows that circuit design choices can have a significant impact on overall fabric/device capabilities required and vice versa. Thereby, we adapt an integrated fabric-circuit exploration methodology. Control schemes for wave streaming and synchronization are also discussed with several SPWF circuit topologies. Our estimations show that significant area and power benefits can be expected for SPWF-based designs versus CMOS. In particular, for a 1-bit adder up to 40X area benefit and up to 304X power consumption reduction may be possible with SPWF-based implementation versus 45 nm CMOS.

scholarly journals Advanced CMOS Gate Stack: Present Research Progress

2012 ◽  
Vol 2012 ◽  
pp. 1-35 ◽  
Author(s):  
Chun Zhao ◽  
C. Z. Zhao ◽  
M. Werner ◽  
S. Taylor ◽  
P. R. Chalker
Keyword(s):  
Electron Tunneling ◽  
Gate Dielectrics ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Research Area ◽  
Atomic Scale ◽  
Oxide Semiconductor ◽  
Research Progress ◽  
Characterization Methods ◽  
Device Reliability

The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor technology require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k). When the SiO2 gate thickness is reduced below 1.4 nm, electron tunneling effects and high leakage currents occur which present serious obstacles for device reliability. In recent years, various alternative gate dielectrics have been researched. Following the introduction of HfO2 into the 45 nm process by Intel in 2007, the screening and selection of high-k gate stacks, understanding their properties, and their integration into CMOS technology have been a very active research area. This paper reviews the progress and efforts made in the recent years for high-k dielectrics, which can be potentially integrated into 22 nm (and beyond) technology nodes. Our work includes deposition techniques, physical characterization methods at the atomic scale, and device reliability as the focus. For most of the materials discussed here, structural and physical properties, dielectric relaxation issues, and projections towards future applications are also discussed.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

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