Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

2012 ◽  
Vol 21 (4) ◽  
pp. 048501 ◽  
Author(s):  
Cong Li ◽  
Yi-Qi Zhuang ◽  
Li Zhang ◽  
Jun-Lin Bao
Keyword(s):  
Analytical Model ◽  
Gate Dielectric ◽  
Lowering Effect ◽  
Surrounding Gate ◽  
Dual Material

scholarly journals Triple Metal Surrounding Gate Junctionless Tunnel FET based 6T SRAM Design For Low Leakage Memory System

2021 ◽  
Author(s):  
G. LAKSHMI PRIYA ◽  
M. VENKATESH ◽  
N.B. BALAMURUGAN ◽  
T.S. ARUN SAMUEL
Keyword(s):  
Analytical Model ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Memory Systems ◽  
Low Leakage ◽  
Tunnel Fet ◽  
High K ◽  
Sram Design ◽  
Surrounding Gate ◽  
Hot Carrier Effects

Abstract The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET)based 6T SRAM structure is demonstrated by employing Germanium (Ge)and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D-TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.

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