scholarly journals A Channel Self-Alignment process for High-Voltage VDMOSFETs in 4H-SiC

2021 ◽  
Vol 2083 (2) ◽  
pp. 022092
Author(s):  
Huan Ge ◽  
Tao Zhu ◽  
Shucheng Chang ◽  
Wanli Zhao ◽  
Xue Bai
Keyword(s):  
High Voltage ◽  
Oxidation Rate ◽  
Silicon Oxide ◽  
Source Region ◽  
Side Wall ◽  
Channel Length ◽  
Pattern Transfer ◽  
N Source ◽  
Alignment Process ◽  
Injection Methods

Abstract In this paper, we describe a channel self-alignment process to produce High-Voltage VDMOSFETs in 4H-SiC. We use polysilicon as a mask for two injection methods, Because the oxidation rate of polysilicon is different from that of silicon carbide, we can generate a certain thickness of silicon oxide flank wall by controlling the oxidation rate and time. Therefore, there will be a certain distance between the N+ source region and the Pbase region, and this distance is the length of the channel. Obviously, no pattern transfer occurs between the two ion implantation processes, so the channel is self-aligned. As long as the thickness of the side wall is controlled accurately, the channel length of sub-micron can be obtained.

Dendritic Growth Failure of a Mesa Diode

1997 ◽  
Author(s):  
P. Singh ◽  
V. Cozzolino ◽  
G. Galyon ◽  
R. Logan ◽  
K. Troccia ◽  
...  
Keyword(s):  
Electric Fields ◽  
Dendritic Growth ◽  
Silicon Oxide ◽  
Impact Ionization ◽  
Electron Tunneling ◽  
Growth Failure ◽  
Side Wall ◽  
Oxide Interface ◽  
Band Bending ◽  
Cross Section Area

Abstract The time delayed failure of a mesa diode is explained on the basis of dendritic growth on the oxide passivated diode side walls. Lead dendrites nucleated at the p+ side Pb-Sn solder metallization and grew towards the n side metallization. The infinitesimal cross section area of the dendrites was not sufficient to allow them to directly affect the electrical behavior of the high voltage power diodes. However, the electric fields associated with the dendrites caused sharp band bending near the silicon-oxide interface leading to electron tunneling across the band gap at velocities high enough to cause impact ionization and ultimately the avalanche breakdown of the diode. Damage was confined to a narrow path on the diode side wall because of the limited influence of the electric field associated with the dendrite. The paper presents experimental details that led to the discovery of the dendrites. The observed failures are explained in the context of classical semiconductor physics and electrochemistry.

scholarly journals Ultimate 0.34 nm Gate-length Side-Wall Transistors with Atomic Level Channel

2020 ◽  
Author(s):  
Tian-Ling Ren ◽  
Fan Wu ◽  
Yang Shen ◽  
He Tian ◽  
Jie Ren ◽  
...  
Keyword(s):  
Side Wall ◽  
Vertical Channel ◽  
Chemical Vapor ◽  
Channel Length ◽  
Atomic Level ◽  
Channel Structure ◽  
Gate Length ◽  
Large Area ◽  
Gate Control ◽  
Chemical Vapor Deposition Graphene

Abstract Despite 55 years of efforts into short gate length transistors following the Moore’s law, the gate length below 1 nm has not been realized. Here, we demonstrated a side-wall monolayer MoS2 transistors with ultimate 0.34 nm gate length using the edge of graphene as gate electrode. Moreover, large area of chemical vapor deposition graphene and MoS2 are used for 2-inch wafer production. These ultrashort devices show excellent ON/OFF current ratio of 2 × 105. Simulation results indicate that the MoS2 side-wall effective channel length approaches 0.34 nm in the ON state. This graphene edge gate combined with MoS2 vertical channel structure provides an efficient gate control ability and enables the physical gate length scaling down to atomic level, which shows great potential to build next generation electronics.

scholarly journals Analisa Rekonfigurasi Jaringan Distribusi 20 kV Pada Penyulang Berawa Untuk Menurunkan Losses dan Drop Tegangan Penyaluran Tenaga Listrik

2019 ◽  
Vol 6 (2) ◽  
pp. 67
Author(s):  
I Gusti Nyoman Indra Wiguna ◽  
I Gede Dyana Arjana ◽  
Tjok. Gede Indra P
Keyword(s):  
High Voltage ◽  
Voltage Drop ◽  
Peak Load ◽  
Channel Length ◽  
Limit Set ◽  
Very High ◽  
Maximum Limit

Peak load on Berawa Feeder is very high exceeding the maximum limit set by PLN which causes Losses and high voltage drop values, so reconfiguration of Repeater via LBS Canggu Club and LBS Damai Residance is carried out, using 3 distribution points. The flow before being reconfigured in the Swamp Feeder was 242A to 180.2A, while the previous Bumbak Feeder was 82A to 144.7A. losses previous deliveries of Bumbak Feederwere 5.2kW to 22.15kW, while previous Berawa Berulang was 117.1kW to 55.11kW, drop the previous Bumbak Feeder voltagewas 102kVA to 24kVA, whereas the previous Swamp Feeder was 775.4kVA to 490.2kVA. Load surges and decreases are caused by changes in load and channel length after being reconfigured.

Properties of high-voltage stress generated traps in thin silicon oxide

1996 ◽  
Vol 43 (7) ◽  
pp. 1133-1143 ◽  
Author(s):  
R.S. Scott ◽  
N.A. Dumin ◽  
T.W. Hughes ◽  
D.J. Dumin ◽  
B.T. Moore
Keyword(s):  
High Voltage ◽  
Silicon Oxide ◽  
Voltage Stress ◽  
Thin Silicon

Current-Voltage Characteristics of Side-Gated Silicon Nanowire Transistor Fabricated by AFM Lithography

2011 ◽  
Vol 277 ◽  
pp. 84-89 ◽  
Author(s):  
Sabar Derita Hutagalung ◽  
Kam C. Lew
Keyword(s):  
Silicon Oxide ◽  
Silicon Nanowire ◽  
Silicon Layer ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Nanowire Transistor ◽  
Relative Air Humidity ◽  
Local Anodic Oxidation ◽  
Channel Thickness ◽  
Afm Lithography

Silicon nanowire transistor (SiNWT) was fabricated by using a silicon nanowire as a channel which directly connected to the source (S) and drain (D). In this work, a side gate (G) formation was used to develop a transistor structure. AFM lithography was performed to create the nanoscale oxide patterns via local anodic oxidation (LAO) mechanism. A conductive AFM tip was used to grow localized oxide layer on the surface of silicon on insulator (SOI) substrate by the application of voltage between tip and substrate. Other parameters that will influence the patterning process such as tip writing speed, relative air humidity, anodization time and substrate orientation were controlled. The patterned structure was etched with tetramethylammonium hydroxide (TMAH) and hydrogen fluoride (HF) acid to remove the uncovered silicon layer and silicon oxide mask patterns, respectively. The surface topography and dimension of the fabricated SiNWT was observed under AFM. Obtained results for the channel thickness, channel length and the distance between the channel and side gate are 32.92 nm, 7.63 µm and 108.07 nm, respectively. Meanwhile, the I-V characteristics of fabricated SiNWT measured at positive gate voltages are similar to p-type FET characteristics.

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