Ultimate 0.34 nm Gate-length Side-Wall Transistors with Atomic Level Channel

Abstract Despite 55 years of efforts into short gate length transistors following the Moore’s law, the gate length below 1 nm has not been realized. Here, we demonstrated a side-wall monolayer MoS2 transistors with ultimate 0.34 nm gate length using the edge of graphene as gate electrode. Moreover, large area of chemical vapor deposition graphene and MoS2 are used for 2-inch wafer production. These ultrashort devices show excellent ON/OFF current ratio of 2 × 105. Simulation results indicate that the MoS2 side-wall effective channel length approaches 0.34 nm in the ON state. This graphene edge gate combined with MoS2 vertical channel structure provides an efficient gate control ability and enables the physical gate length scaling down to atomic level, which shows great potential to build next generation electronics.

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100-nm Channel Length a-Si:H Vertical Thin Film Transistors

MRS Proceedings ◽

10.1557/proc-814-i2.4/a3.4 ◽

2004 ◽

Vol 814 ◽

Author(s):

Isaac Chan ◽

Arokia Nathan

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Vertical Channel ◽

Channel Length ◽

Channel Structure ◽

Large Area ◽

Short Channel ◽

Low Leakage ◽

Low Leakage Current ◽

Channel Effects

AbstractThis paper reports on hydrogenated amorphous silicon (a-Si:H) vertical thin film transistors (VTFTs) with channel length of 100 nm, using conventional planar TFT processing technology. The device has a fully self-aligned vertical channel structure, which is highly insensitive to the non-uniformity of reactive ion etching (RIE). Therefore, the VTFT process is very suitable for large-area electronics. Presently, we can demonstrate VTFTs with remarkable ON/OFF current ratio of more than 108, low leakage current down to 1 fA, and good subthreshold slope of 0.8 V/dec at Vd = 1.5 V. The impacts of contemporary device issues, such as short-channel effects and contact resistance, on the performance of short-channel VTFTs and suggested avenues for improvement are discussed.

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Imaging of local structures affecting electrical transport properties of large graphene sheets by lock-in thermography

Science Advances ◽

10.1126/sciadv.aau3407 ◽

2019 ◽

Vol 5 (2) ◽

pp. eaau3407 ◽

Cited By ~ 12

Author(s):

H. Nakajima ◽

T. Morimoto ◽

Y. Okigawa ◽

T. Yamada ◽

Y. Ikuta ◽

...

Keyword(s):

Transport Properties ◽

Electrical Transport ◽

Chemical Vapor ◽

Atomic Scale ◽

Electrical Transport Properties ◽

Large Area ◽

Graphene Layers ◽

Device Applications ◽

Chemical Vapor Deposition Graphene ◽

Lock In

The distribution of defects and dislocations in graphene layers has become a very important concern with regard to the electrical and electronic transport properties of device applications. Although several experiments have shown the influence of defects on the electrical properties of graphene, these studies were limited to measuring microscopic areas because of their long measurement times. Here, we successfully imaged various local defects in a large area of chemical vapor deposition graphene within a reasonable amount of time by using lock-in thermography (LIT). The differences in electrical resistance caused by the micrometer-scale defects, such as cracks and wrinkles, and atomic-scale domain boundaries were apparent as nonuniform Joule heating on polycrystalline and epitaxially grown graphene. The present results indicate that LIT can serve as a fast and effective method of evaluating the quality and uniformity of large graphene films for device applications.

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Thermodynamics Controlled Sharp Transformation from InP to GaP Nanowires via Introducing Trace Amount of Gallium

Nanoscale Research Letters ◽

10.1186/s11671-021-03505-2 ◽

2021 ◽

Vol 16 (1) ◽

Author(s):

Zhenzhen Tian ◽

Xiaoming Yuan ◽

Ziran Zhang ◽

Wuao Jia ◽

Jian Zhou ◽

...

Keyword(s):

Chemical Vapor Deposition ◽

Vapor Deposition ◽

Driving Force ◽

Chemical Vapor ◽

Chemical Vapor Deposition Method ◽

Nanowire Growth ◽

Calphad Approach ◽

Deposition Method ◽

Large Area ◽

Growth Phenomenon

AbstractGrowth of high-quality III–V nanowires at a low cost for optoelectronic and electronic applications is a long-term pursuit of research. Still, controlled synthesis of III–V nanowires using chemical vapor deposition method is challenge and lack theory guidance. Here, we show the growth of InP and GaP nanowires in a large area with a high density using a vacuum chemical vapor deposition method. It is revealed that high growth temperature is required to avoid oxide formation and increase the crystal purity of InP nanowires. Introduction of a small amount of Ga into the reactor leads to the formation of GaP nanowires instead of ternary InGaP nanowires. Thermodynamic calculation within the calculation of phase diagrams (CALPHAD) approach is applied to explain this novel growth phenomenon. Composition and driving force calculations of the solidification process demonstrate that only 1 at.% of Ga in the catalyst is enough to tune the nanowire formation from InP to GaP, since GaP nucleation shows a much larger driving force. The combined thermodynamic studies together with III–V nanowire growth studies provide an excellent example to guide the nanowire growth.

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Impact of device scaling on the electrical properties of MoS2 field-effect transistors

Scientific Reports ◽

10.1038/s41598-021-85968-y ◽

2021 ◽

Vol 11 (1) ◽

Author(s):

Goutham Arutchelvan ◽

Quentin Smets ◽

Devin Verreck ◽

Zubair Ahmed ◽

Abhinav Gaur ◽

...

Keyword(s):

Field Effect Transistors ◽

Oxide Thickness ◽

Channel Length ◽

Contact Length ◽

Power Performance ◽

Semiconducting Materials ◽

Large Area ◽

Short Channel ◽

Device Scaling ◽

Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

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Vertical channel structure strategy in competing supply chains under third party’s extended warranties based on inverse demand function

2020 Management Science Informatization and Economic Innovation Development Conference (MSIEID) ◽

10.1109/msieid52046.2020.00113 ◽

2020 ◽

Author(s):

Lei Zhang ◽

Jianhua Ma

Keyword(s):

Supply Chains ◽

Demand Function ◽

Vertical Channel ◽

Channel Structure ◽

Extended Warranties ◽

Inverse Demand

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Practical Route for the Low-Temperature Growth of Large-Area Bilayer Graphene on Polycrystalline Nickel by Cold-Wall Chemical Vapor Deposition

ACS Omega ◽

10.1021/acsomega.1c00841 ◽

2021 ◽

Author(s):

Muhammad Aniq Shazni Mohammad Haniff ◽

Nur Hamizah Zainal Ariffin ◽

Poh Choon Ooi ◽

Mohd Farhanulhakim Mohd Razip Wee ◽

Mohd Ambri Mohamed ◽

...

Keyword(s):

Chemical Vapor Deposition ◽

Low Temperature ◽

Vapor Deposition ◽

Chemical Vapor ◽

Bilayer Graphene ◽

Cold Wall ◽

Polycrystalline Nickel ◽

Large Area ◽

Temperature Growth ◽

Low Temperature Growth

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The Photodetectors Based on Lateral Monolayer MoS2/WS2 Heterojunctions

Nanoscale Research Letters ◽

10.1186/s11671-021-03581-4 ◽

2021 ◽

Vol 16 (1) ◽

Author(s):

Caihong Li ◽

Juntong Zhu ◽

Wen Du ◽

Yixuan Huang ◽

Hao Xu ◽

...

Keyword(s):

Communication Systems ◽

Transition Metal Dichalcogenides ◽

Chemical Vapor ◽

Large Area ◽

Optical Signals ◽

Metal Dichalcogenides ◽

One Step ◽

The One ◽

Charge Carrier Trapping ◽

Sharp Interfaces

AbstractMonolayer transition metal dichalcogenides (TMDs) show promising potential for next-generation optoelectronics due to excellent light capturing and photodetection capabilities. Photodetectors, as important components of sensing, imaging and communication systems, are able to perceive and convert optical signals to electrical signals. Herein, the large-area and high-quality lateral monolayer MoS2/WS2 heterojunctions were synthesized via the one-step liquid-phase chemical vapor deposition approach. Systematic characterization measurements have verified good uniformity and sharp interfaces of the channel materials. As a result, the photodetectors enhanced by the photogating effect can deliver competitive performance, including responsivity of ~ 567.6 A/W and detectivity of ~ 7.17 × 1011 Jones. In addition, the 1/f noise obtained from the current power spectrum is not conductive to the development of photodetectors, which is considered as originating from charge carrier trapping/detrapping. Therefore, this work may contribute to efficient optoelectronic devices based on lateral monolayer TMD heterostructures.

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All-Organic, Low Voltage, Transparent and Compliant Organic Field-Effect Transistor Fabricated by Means of Large-Area, Cost-Effective Techniques

Applied Sciences ◽

10.3390/app10196656 ◽

2020 ◽

Vol 10 (19) ◽

pp. 6656

Author(s):

Stefano Lai ◽

Giulia Casula ◽

Pier Carlo Ricci ◽

Piero Cosseddu ◽

Annalisa Bonfiglio

Keyword(s):

Field Effect ◽

Low Voltage ◽

Field Effect Transistors ◽

High Mobility ◽

Chemical Vapor ◽

Cost Effective ◽

Large Area ◽

Parylene C ◽

Biomedical Sensing ◽

Novel Applications

The development of electronic devices with enhanced properties of transparency and conformability is of high interest for the development of novel applications in the field of bioelectronics and biomedical sensing. Here, a fabrication process for all organic Organic Field-Effect Transistors (OFETs) by means of large-area, cost-effective techniques such as inkjet printing and chemical vapor deposition is reported. The fabricated device can operate at low voltages (as high as 4 V) with ideal electronic characteristics, including low threshold voltage, relatively high mobility and low subthreshold voltages. The employment of organic materials such as Parylene C, PEDOT:PSS and 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS pentacene) helps to obtain highly transparent transistors, with a relative transmittance exceeding 80%. Interestingly enough, the proposed process can be reliably employed for OFET fabrication over different kind of substrates, ranging from transparent, flexible but relatively thick polyethylene terephthalate (PET) substrates to transparent, 700-nm-thick, compliant Parylene C films. OFETs fabricated on such sub-micrometrical substrates maintain their functionality after being transferred onto complex surfaces, such as human skin and wearable items. To this aim, the electrical and electromechanical stability of proposed devices will be discussed.

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