Improved PECVD SixNyfilm as a mask layer for deep wet etching of the silicon

2017 ◽  
Vol 4 (9) ◽  
pp. 096301
Author(s):  
Jianqiang Han ◽  
Yi Jun Yin ◽  
Dong Han ◽  
LiZhen Dong
Keyword(s):  
Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 136
Author(s):  
Yiingqi Shang ◽  
Hongquan Zhang ◽  
Yan Zhang

Aimed at the problem of the small wet etching depth in sapphire microstructure processing technology, a multilayer composite mask layer is proposed. The thickness of the mask layer is studied, combined with the corrosion rate of different materials on sapphire in the sapphire etching solution, different mask layers are selected for the corrosion test on the sapphire sheet, and then the corrosion experiment is carried out. The results show that at 250 °C, the choice is relatively high when PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to make a double-layer composite film of silicon dioxide and silicon nitride. When the temperature rises to 300 °C, the selection ratio of the silicon dioxide layer grown by PECVD is much greater than that of the silicon nitride layer. Therefore, under high temperature conditions, a certain thickness of silicon dioxide can be used as a mask layer for deep cavity corrosion.


2014 ◽  
Vol 526 ◽  
pp. 80-85
Author(s):  
Ze Long Zhou ◽  
Chen Mei ◽  
Xiang Yong Su ◽  
Tao Li ◽  
Yi Tao

Simplex wet etching method to fabricate silicon-beam has limited the categories of silicon-beam, it has confined the design and fabrication of silicon-beam with polygon section. Moreover, due to the side-etching of sidewalls and arris during the process of wet etching, the sections of the fabricated silicon-beam are not identical, which will induce the mechanics characters of silicon-beam to be altered, depressing the quality of silicon-beam; In order to avoid the shortages above, a novel method to fabricate silicon-beam with polygon section based on thermal oxidation layer technique is proposed, thermal oxidation SiO2 layer is utilized as the protection layer of the sidewalls of the silicon-beam instead of the mask layer as usual for the first time. Combining the wet etching technique with the thermal oxidation technique innovatively, several varieties of silicon-beam with polygon section, which can hardly be obtained only by the use of wet etching technique, can be manufactured, respectively. Based on such an innovative method, this paper proposes and develops five varieties of silicon-beam with novel structure by means of adjustable mask layer, extending the application field of wet etching. The subsequent fabrication experiment of silicon-beam with hexagonal section has been taken as an example to validate the technique principle. The dimension parameters of silicon-beam have been tested precisely and the arris angle error between the theoretic value and the experimental measurement is less than 1.5%; The SEM photos with the amplifier of 100 and 250 have been obtained through HITACHI S-4800 field emission scanning electron microscope (FE-SEM), the SEM results have demonstrated the clear sidewall arris without undercut. Through this fabrication method, the sidewall arris of silicon-beam can be maintained due to the protection layer of thermal oxidation SiO2. In this manner, the arris disfigurement of the silicon-beam decreases dramatically, the process of etching can be controlled precisely, and the quality of the silicon-beam has been improved greatly.


Author(s):  
Hiroyuki Niino ◽  
Tadatake Sato ◽  
Yoshizo Kawaguchi ◽  
Aiko Narazaki ◽  
Ryozo Kurosaki
Keyword(s):  

Author(s):  
T.W. Lee

Abstract WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.


Author(s):  
Tomokazu Nakai

Abstract Currently many methods are available to obtain a junction profile of semiconductor devices, but the conventional methods have drawbacks, and they could be obstacles for junction profile analysis. This paper introduces an anodic wet etching-based two-dimensional junction profiling method, which is practical, efficient, and reliable for failure analysis and electrical characteristics evaluation.


Nanomaterials ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 783
Author(s):  
Jeeyoon Jeong ◽  
Hyosim Yang ◽  
Seondo Park ◽  
Yun Daniel Park ◽  
Dai-Sik Kim

A metallic nano-trench is a unique optical structure capable of ultrasensitive detection of molecules, active modulation as well as potential electrochemical applications. Recently, wet-etching the dielectrics of metal–insulator–metal structures has emerged as a reliable method of creating optically active metallic nano-trenches with a gap width of 10 nm or less, opening a new venue for studying the dynamics of nanoconfined molecules. Yet, the high surface tension of water in the process of drying leaves the nano-trenches vulnerable to collapsing, limiting the achievable width to no less than 5 nm. In this work, we overcome the technical limit and realize metallic nano-trenches with widths as small as 1.5 nm. The critical point drying technique significantly alleviates the stress applied to the gap in the drying process, keeping the ultra-narrow gap from collapsing. Terahertz spectroscopy of the trenches clearly reveals the signature of successful wet etching of the dielectrics without apparent damage to the gap. We expect that our work will enable various optical and electrochemical studies at a few-molecules-thick level.


Author(s):  
Yang Liu ◽  
Lai Wang ◽  
Yuantao Zhang ◽  
Xin Dong ◽  
Zhibiao Hao ◽  
...  
Keyword(s):  

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