On-chip Slot Ring Antenna Integrated with Voltage Controlled Oscillator at 140 GHz in 40nm CMOS Technology

2019 ◽  
Author(s):  
Wei-Kai Chen ◽  
Yu-Teng Chang ◽  
Hsin-Chia Lu
Keyword(s):  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Ring Antenna ◽  
On Chip

scholarly journals A system-on-chip 1.5 GHz phase locked loop realized using 40 nm CMOS technology

2018 ◽  
Vol 31 (1) ◽  
pp. 101-113
Author(s):  
Weiyin Wang ◽  
Xiangjie Chen ◽  
Hei Wong
Keyword(s):  
Cmos Technology ◽  
System On Chip ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Sigma Delta ◽  
Fully Integrated ◽  
Measurement Results ◽  
Feedback Structure ◽  
On Chip ◽  
Frequency Detector

This work presents the design and realization of a fully-integrated 1.5 GHz sigma-delta fractional-N ring-based PLL for system-on-chip (SoC) applications. Some design optimizations were conducted to improve the performance of each functional block such as phase frequency detector (PFD), voltage-controlled oscillator (VCO), filter and charge pump (CP) and so as for the whole system. In particular, a time delay circuit is designed for overcoming the blind zone in the PFD; an operational amplifier-feedback structure was used to eliminate the current mismatch in the CP, a 3rd LPF is used for suppressing noises and a current overdrive structure is used in VCO design. The design was realized with a commercial 40 nm CMOS process. The core die sized about 0.041 mm2. Measurement results indicated that the circuit functions well for the locked range between 500 MHz to 1.5 GHz.

Coherent J-Band radiating arrays based on ×27 CMOS activemultiplier chips

2019 ◽  
Vol 11 (08) ◽  
pp. 747-754
Author(s):  
Roman Klimovich ◽  
Samuel Jameson ◽  
Eran Socher
Keyword(s):  
Printed Circuit Board ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Power Dividers ◽  
Radiated Power ◽  
Ring Antenna ◽  
On Chip ◽  
Practical Factors

AbstractThis paper presents a hybrid design of 1 × 2 and 1 × 4 arrays operating in 0.277–0.292 THz on 65 nm Complementary metal–oxide–semiconductor (CMOS) technology. Each of the chips has an X-band input with 3 ×3 multiplier stages and connected at the output to an on-chip ring antenna. A wideband microstrip Wilkinson four-way and two-way power dividers have been developed on a multilayer printed circuit board to feed the array elements with proper radio frequency and direct current inputs. Demonstrating improvements in effective isotropically radiated power and in total radiated power compared to a single CMOS element, the hybrid integration approach proves effective in implementing coherent THz transmitter arrays. Theoretical and practical factors that reduce the radiated power compared with ideal arrays are also discussed.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

scholarly journals A Tunable-Gain Transimpedance Amplifier for CMOS-MEMS Resonators Characterization

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 82
Author(s):  
Rafel Perelló-Roig ◽  
Jaume Verd ◽  
Sebastià Bota ◽  
Jaume Segura
Keyword(s):  
Cmos Technology ◽  
Open Loop ◽  
Transimpedance Amplifier ◽  
Mems Devices ◽  
Monolithically Integrated ◽  
Mems Resonators ◽  
Electromechanical Performance ◽  
Cmos Mems ◽  
Promising Solution ◽  
On Chip

CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical performance otherwise achieved by specific technologies, requiring a challenging readout circuitry. This paper presents a transimpedance amplifier (TIA) fabricated using a commercial 0.35-µm CMOS technology specifically oriented to drive and sense monolithically integrated CMOS-MEMS resonators up to 50 MHz with a tunable transimpedance gain ranging from 112 dB to 121 dB. The output voltage noise is as low as 225 nV/Hz1/2—input-referred current noise of 192 fA/Hz1/2—at 10 MHz, and the power consumption is kept below 1-mW. In addition, the TIA amplifier exhibits an open-loop gain independent of the parasitic input capacitance—mostly associated with the MEMS layout—representing an advantage in MEMS testing compared to other alternatives such as Pierce oscillator schemes. The work presented includes the characterization of three types of MEMS resonators that have been fabricated and experimentally characterized both in open-loop and self-sustained configurations using the integrated TIA amplifier. The experimental characterization includes an accurate extraction of the electromechanical parameters for the three fabricated structures that enables an accurate MEMS-CMOS circuitry co-design.

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

P-45: On-Chip ESD Protection Design for UXGA/HDTV LCoS in 0.35-μm CMOS Technology

2004 ◽  
Vol 35 (1) ◽  
pp. 404
Author(s):  
Ming-Dou Ker ◽  
Shih-Hung Chen ◽  
Tang-Kui Tseng
Keyword(s):  
Cmos Technology ◽  
Esd Protection ◽  
On Chip
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